From f9b72572c8d5b6d312fd0b5014f65bed20efac40 Mon Sep 17 00:00:00 2001 From: Deepak Sharma Date: Thu, 1 Oct 2026 10:00:35 +0200 Subject: [PATCH] x86/ACPI: optimise C3 entry on AMD CPUs All Zen or newer CPU which support C3 shares cache. Its not necessary to flush the caches in software before entering C3. This will cause drop in performance for the cores which share some caches. ARB_DIS is not used with current AMD C state implementation. So set related flags correctly. Signed-off-by: Deepak Sharma Acked-by: Thomas Gleixner Signed-off-by: Rafael J. Wysocki Origin: https://git.kernel.org/torvalds/p/a8fb40966f19 [Port to Xen. Include Hygon.] Assisted-by: Claude-Code:claude-opus-5-5 Signed-off-by: Olivier Lambert Reviewed-by: Jason Andryuk Acked-by: Jan Beulich --- xen/arch/x86/acpi/cpu_idle.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index 56b22a2ff3..b2bca4dcf8 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -1065,6 +1065,24 @@ static void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flag */ if ( c->vendor == X86_VENDOR_INTEL ) flags->bm_control = 0; + + if ( (c->vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) && + c->family >= 0x17 ) + { + /* + * For all AMD Zen or newer CPUs that support C3, caches + * should not be flushed by software while entering C3 + * type state. Set bm_check to 1 so that Xen doesn't + * need to execute cache flush operation. + */ + flags->bm_check = 1; + /* + * In current AMD C state implementation ARB_DIS is no longer + * used. So set bm_control to zero to indicate ARB_DIS is not + * required while entering C3 type state. + */ + flags->bm_control = 0; + } } #define VENDOR_INTEL (1)