Commit Graph
24 Commits
Author SHA1 Message Date
Ian Campbell 443701ef0c Replace FSF street address with canonical URL
As recommended in http://www.gnu.org/licenses/gpl-howto.en.html.

This is the result of:
$ git grep -El Mass\|Temple\|Franklin | xargs ./fsf.pl

Where fsf.pl is:
    #!/usr/bin/perl -w -pi.bak -0777
    my $repl = 'If not, see <http://www.gnu.org/licenses/>.';
    my $br = qr/(?:\s*\n\s*(?:[\*\#]|\/\/|\.\\" )?\s*|\s+)/;

    my $inwt = qr/[Ii]f${br}not,${br}write${br}(?:to${br})?the${br}Free${br}Software${br}Foundation,(?:${br}Inc\.,)?/;

    my $mass = qr/675${br}Mass${br}Ave,?${br}Cambridge,?${br}MA${br}02139,?${br}USA,?\.?/;
    my $franklin = qr/51${br}Franklin${br}St(?:reet)?(?:,${br}| - )Fifth${br}Floor,?${br}Boston,?${br}MA,?${br}02110-1301,?${br}USA,?\.?/;
    my $temple = qr/59${br}Temple${br}Place(?:,${br}| - )Suite${br}330,?${br}Boston,?${br}MA,?${br}021110?-1307,?${br}USA,?\.?/;

    s|$inwt$br$mass|$repl|m;
    s|$inwt$br$franklin|$repl|m;
    s|$inwt$br$temple|$repl|m;

The only remaining mentions of these addresses are in COPYING files which I
haven't touched.

Some of the changed files are imports from elsewhere, however
filtering them out is tricky, I think it is tolerable to have these
files be modified here and then perhaps reverted on the next sync,
since it's only 1-2 lines and obvious what is going on.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
2015-07-29 11:14:07 +01:00
Feng Wu 953282a099 x86/tools: expose SMAP to HVM guests
This patch exposes SMAP festure to HVM guests

Signed-off-by: Feng Wu <feng.wu@intel.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
2014-05-12 17:05:33 +02:00
Jan Beulich c097f54912 x86/SVM: support data breakpoint extension registers
Leveraging the generic MSR save/restore logic introduced a little while
ago.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Tested-by: Aravind Gopalakrishnan<aravind.gopalakrishnan@amd.com>
Reviewed-by: George Dunlap <george.dunlap@eu.citrix.com>
Reviewed-by: Aravind Gopalakrishnan<aravind.gopalakrishnan@amd.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
2014-04-24 10:51:21 +02:00
Liu Jinsong 62060f3227 libxc: X86: expose RDSEED, ADX, and PREFETCHW to pv/hvm
Intel recently released some new features, including RDSEED, ADX, and
PREFETCHW.  This patch exposes these new features to pv and hvm.

Signed-off-by: Xudong Hao <xudong.hao@intel.com>
Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
2014-04-08 15:41:42 +01:00
Liu, Jinsong 6fd5f43ad9 x86: Expose TSC adjust to HVM guest
Intel latest SDM (17.13.3) release a new MSR CPUID.7.0.EBX[1]=1
indicates TSC_ADJUST MSR 0x3b is supported.

This patch expose it to hvm guest.

Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
Committed-by: Jan Beulich <jbeulich@suse.com>
2012-09-26 12:14:30 +02:00
Liu, Jinsong db730e2b4f x86,tools/libxc: expose HLE/RTM features to pv and hvm
Intel recently release 2 new features, HLE and TRM.
Refer to http://software.intel.com/file/41417.
This patch expose them to pv and hvm

Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
Committed-by: Keir Fraser <keir@xen.org>
2012-03-01 16:31:52 +00:00
Liu, Jinsong 7de3c6981c X86: Disable PCID/INVPCID for pv
This patch disable PCID/INVPCID for pv.

Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
Committed-by: Keir Fraser <keir@xen.org>
2011-12-06 11:28:04 +00:00
Liu, Jinsong 25050f53be X86: expose Intel new features to pv/hvm
Intel recently release some new features, including
FMA/AVX2/BMI1/BMI2/LZCNT/MOVBE.
Refer to http://software.intel.com/file/36945
This patch expose these new features to pv and hvm.

Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
Committed-by: Keir Fraser <keir@xen.org>
2011-12-06 11:27:18 +00:00
Yang, Wei d3b35446fd x86: Pass through ERMS CPUID feature for HVM and PV guests
This patch exposes ERMS feature to HVM and PV guests.

The REP MOVSB/STOSB instruction can enhance fast strings attempts to
move as much of the data with larger size load/stores as possible.

Signed-off-by: Yang, Wei <wei.y.yang@intel.com>
2011-06-14 13:13:18 +01:00
Yang, Wei 30090ad856 x86/hvm: Make DRNG feature visible in CPUID
This patch exposes DRNG feature to HVM guests.

The RDRAND instruction can provide software with sequences of
random numbers generated from white noise.

Signed-off-by: Yang, Wei <wei.y.yang@intel.com>
2011-06-14 12:44:48 +01:00
Tim Deegan 89c9f78710 x86/hvm: add SMEP support to HVM guest
Intel new CPU supports SMEP (Supervisor Mode Execution Protection). SMEP
prevents software operating with CPL < 3 (supervisor mode) from fetching
instructions from any linear address with a valid translation for which the U/S
flag (bit 2) is 1 in every paging-structure entry controlling the translation
for the linear address.

This patch adds SMEP support to HVM guest.

Signed-off-by: Yang Wei <wei.y.yang@intel.com>
Signed-off-by: Shan Haitao <haitao.shan@intel.com>
Signed-off-by: Li Xin <xin.li@intel.com>
Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
2011-06-06 13:46:48 +01:00
Keir Fraser 997f96a28b libxc: Don't refer to meaningless 'word offsets' in xc_cpufeature.h
Signed-off-by: Keir Fraser <keir@xen.org>
2011-06-03 17:27:01 +01:00
Keir Fraser 0f0230e4fb libxc: Simplify and clean up xc_cpufeature.h
* Remove Linux-private defns with no direct relation to CPUID
 * Remove word offsets into Linux-defined cpu_caps array
 * Hard tabs -> soft tabs

Signed-off-by: Keir Fraser <keir@xen.org>
2011-06-02 15:01:04 +01:00
Keir Fraser 72cc91540e x86: Hide CPUID leaf 7 from PV guests.
Except for the whitelisted FSGSBASE feature.

Signed-off-by: Keir Fraser <keir@xen.org>
2011-06-02 14:39:50 +01:00
Keir Fraser 0145b0e442 hvm: allow pass-through of new FPU/ALU CPUID features
there are some new CPUID features that are safe for guests to see, as
they don't require OS awareness (FPU/ALU related instructions only).
Among features for new AMD CPUs there is also the PCLMULQDQ bit, which
Intel CPU have already for quite a while.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
2011-01-27 16:17:27 +00:00
Keir Fraser c458f45d2e libxc: Update AMD CPU feature flags 0x80000001:ECX for Xen tools
This patch syncs-up AMD CPU feature flags 0x80000001:ECX in libxc with
the latest Linux kernel.

Signed-off-by: Wei Huang <wei.huang2@amd.com>
2011-01-08 10:48:09 +00:00
Keir Fraser d4f5ff0682 x86 hvm: Expose TSC_DEADLINE CPU feature to guests via CPUID.
Signed-off-by: Wei Gang <gang.wei@intel.com>
2010-12-15 11:09:02 +00:00
Keir Fraser 21c4d089ba x86 hvm: x2APIC emulation
This patch would enable Xen to handle x2APIC MSR accessing of HVM
guest, which is faster(avoid decoding of MMIO accessing). The credit
comes to Gleb Natapov who complete the work for KVM.

Have tested with 4 vcpus guest, with/without x2apic support.

From: Sheng Yang <sheng.yang@intel.com>
Signed-off-by: Keir Fraser <keir@xen.org>
2010-12-07 18:24:12 +00:00
Keir Fraser 5a4cecd828 x86 hvm: exposes AVX to guest.
Signed-off-by: Shan Haitao <haitao.shan@intel.com>
Signed-off-by: Han Weidong <weidong.han@intel.com>
2010-11-03 08:16:47 +00:00
Ian Campbell 6993e9f5ce # HG changeset patch
# User Ian Campbell <ian.campbell@citrix.com>
# Date 1282671421 -3600
# Node ID d1dd29a470ef1b9d2c77478a123326036dfe90bb
# Parent  d7a4adad9c328decbd384d87b23001aea8951b86
tools/libxc, tools/libelf: Relicense under LGPL v2.1

Relicense these two libraries under LGPL v2.1 only except where
individual files already included the "or later" provision.

Copyright holders have been contacted by Stephen Spector and have all
agreed this change.

Removed tools/libxc/ia64/aclinux.h since it appeared to be
unused. There is a separate, more up to date, copy in
xen/include/acpi/platform/aclinux.h which does appear to be used.

Clarify the license of MiniOS privcmd.h under the same terms as other
tools/include/xen-sys headers.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Stephen Spector <stephen.spector@citrix.com>
Signed-off-by: Ian Jackson <ian.jackson@eu.citrix.com>
2010-08-24 18:42:59 +01:00
Keir Fraser df54af7dd1 hvm: Extend the CPUID whitelist to include Intel's AES-NI intructions
Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
2010-05-26 08:02:33 +01:00
Keir Fraser 5269962096 x86: Mask X86_FEATURE_XSAVE in cpuid leaf 1, ecx, as we don't allow
guests to use it (by setting cr4.OSXSAVE).

This prevents crashes in pvops kernels, as new versions of Linux
try to use this feature.

Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
2009-03-09 08:54:19 +00:00
Keir Fraser ceb1434f7d x86: support CPUID hypervisor feature bit
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
2008-11-19 16:10:39 +00:00
Keir Fraser 5f14a87ceb x86, hvm: Guest CPUID configuration.
CPUID's replies are now pre-calculated in libxc and given to the
hypervisor via a new domctl.

There are two parts to this feature:
   - We can overwrite cpuid's replies.
   - We can check that a vm is compatible with a host's processor.

Signed-off-by: Jean Guyader <jean.guyader@eu.citrix.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
2008-04-25 13:44:45 +01:00