- portability fix in Makefile: mkhex is not bash specific
- GNU od separates column with one blank, BSD od uses eight blanks.
Change sed to deal with this.
- Add a fourth sed to fix a build error on NetBSD
Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
Once the presence of LPT1 is baked into a Windows guest, it gets upset
if it is subsequently removed. Hence we add the 'LTP1' device object
back into the ACPI DSDT, and remove IRQ 7 from the list of IRQs usable
by the PCI-ISA links.
Signed-off-by: Keir Fraser <keir@xensource.com>
It turns out that although PIIX4 hardware defines the S5 type code to
be 000, all OSes will discover the correct code by evlauating an \_Sx
object in the ACPI DSDT. And we set the type code in that object to be
111.
So this patch keeps the other cleanups made to the piix4acpi.c file,
but switches back to checking for code 111. It also makes it clearer
in both the ioemu code and in the dsdt source code where these magic
numbers come from.
Let's hope noone actually has the true PIIX4 type codes hardcoded
(it's highly doubtful that anyone would).
Signed-off-by: Keir Fraser <keir@xensource.com>
FADT only to XSDT. It avoids a buffer overflow in the initialization
of Window 2000 ACPI HAL (pre ACPI 2.0 OS), and thus enables the
installation and boot. This compatibility practice is also used in
hardware, please refer to:
http://www.acpi.info/presentations/S01USMOBS169_OS%20new.ppt
Signed-off-by: Qing He <qing.he@intel.com>
definition from the ACPI DSDT. This avoids conflict with FDC on IRQ6
(it is a bit more likely that someone will want to connect a floppy
image to a guest than it is that anyone will ever care about
parallel-port functionality).
Signed-off-by: Keir Fraser <keir@xensource.com>
compiled with gcc and linked into the hvmloader as a byte-array.
Hvmloader allocates memory (rounded up to next 64kb) from the e820
table
below 4GB, copies and relocates the 32bit code in the allocated area
and
copies a jumptable (located in a section '.biosjumptable') pointing to
the 'exported' functions into the Bochs BIOS's memory area to link the
two code sections. The memory area has been reserved and can be
identified with the signature '___JMPT'.
In the Bochs BIOS only stub functions are provided. These load the
index
of a particular function in the jump table, switch to protected mode
and
call the function in the high memory area. The stack is prepared such
that functions compiled by gcc can just pick the parameters from the
stack as usual - this means that the 16bit real-mode return address is
taken off the stack. The stub functions should have the same signature
as those in 32bit space. For ABI compatibility reasons parameters
inside
the Bochs BIOS stubs should all be 32bit wide.
This patch includes a test function that calls three gcc-compiled
functions in the high memory area and displays their success status.
Simple tests are done doing multiplication and addition of 32-bit
numbers and reading and modification of a static variable. These
functions test the interface and the relocation code. The test code is
removed in patch part 3.
Signed-off-by: Stefan Berger <stefanb@us.ibm.com>
This is a built-in assumption of HPET 'legacy' IRQ routing, which is
why we have changed to this routing strategy now.
Signed-off-by: Keir Fraser <keir@xensource.com>
for the RSDP in memory (up to the BIOS) rather than calculating its
start address. Recent changes seem to have moved the RSDP to another
location in memory so that I received 'BAD RSPD signature' messages.
I have also fixed some other possible issues related to return codes
and alignment of ACPI entries.
Signed-off-by: Stefan Berger <stefanb@us.ibm.com>
Also simplify the HVM builder interface by doing more work in
the python wrapper, and fix mapping of shared_info page after the
change to map foreign pages by GMFN rather than MFN.
Signed-off-by: Keir Fraser <keir@xensource.com>
Actually the conflict between LAPIC ID 0x00 and IOAPIC ID 0x00
really doesn't matter even in a native system but we can avoid
any risk of a warning by shifting the LAPIC ID space by one.
Also the changeset fixes construction of the MADT (LAPIC info
was overwriting the IOAPIC info) so we can now boot with ACPI
MADT again.
Signed-off-by: Keir Fraser <keir@xensource.com>
1. Override ISA IRQs 5,6,10,11 as active-low level-triggered.
These are 'wired' to PCI devices.
2. Limit PCI-ISA link routers to route to 5,6,10,11. Others
are active-high edge-triggered and so invalid to use for
PCI devices. In any case, four ISA IRQs is sufficient to
avoid unnecessary aliasing among four links.
Also remove PCI device 0 IRQ info. It's an embedded host bridge with
no interrupt sources.
Signed-off-by: Keir Fraser <keir@xensource.com>
TODO:
1. Fix IO-APIC ID to not conflict with LAPIC IDS.
2. Fix i8259 device model (seems to work already though!).
3. Add INTSRC overrides in MPBIOS and ACPI tables so
that PCI legacy IRQ routing always ends up at an
IO-APIC input with level trigger. Restricting link
routing to {5,6,10,11} and setting overrides for all
four of those would work.
Signed-off-by: Keir Fraser <keir@xensource.com>
Avoids possible vga driver loading problem in HVM Windows guest.
Also fixes a Makefile bug in hvmloader directory.
Signed-off-by: Qing He <qing.he@intel.com>
and extra code in hvm_vcpu_initialise(). Remove 'apic' config
option -- HVM CPUs will always have an APIC (which should be
set up in virtual wire mode for backward compatibility, just as
in a real system).
Signed-off-by: Keir Fraser <keir@xensource.com>
directory pending tighter integration of table generation
into hvmloader. This patch also includes the TPM TIS SSDT
generator from Stefan Berger at IBM.
Signed-off-by: Keir Fraser <keir@xensource.com>
