This is a built-in assumption of HPET 'legacy' IRQ routing, which is
why we have changed to this routing strategy now.
Signed-off-by: Keir Fraser <keir@xensource.com>
Also simplify the HVM builder interface by doing more work in
the python wrapper, and fix mapping of shared_info page after the
change to map foreign pages by GMFN rather than MFN.
Signed-off-by: Keir Fraser <keir@xensource.com>
Actually the conflict between LAPIC ID 0x00 and IOAPIC ID 0x00
really doesn't matter even in a native system but we can avoid
any risk of a warning by shifting the LAPIC ID space by one.
Also the changeset fixes construction of the MADT (LAPIC info
was overwriting the IOAPIC info) so we can now boot with ACPI
MADT again.
Signed-off-by: Keir Fraser <keir@xensource.com>
1. Override ISA IRQs 5,6,10,11 as active-low level-triggered.
These are 'wired' to PCI devices.
2. Limit PCI-ISA link routers to route to 5,6,10,11. Others
are active-high edge-triggered and so invalid to use for
PCI devices. In any case, four ISA IRQs is sufficient to
avoid unnecessary aliasing among four links.
Also remove PCI device 0 IRQ info. It's an embedded host bridge with
no interrupt sources.
Signed-off-by: Keir Fraser <keir@xensource.com>
TODO:
1. Fix IO-APIC ID to not conflict with LAPIC IDS.
2. Fix i8259 device model (seems to work already though!).
3. Add INTSRC overrides in MPBIOS and ACPI tables so
that PCI legacy IRQ routing always ends up at an
IO-APIC input with level trigger. Restricting link
routing to {5,6,10,11} and setting overrides for all
four of those would work.
Signed-off-by: Keir Fraser <keir@xensource.com>
Avoids possible vga driver loading problem in HVM Windows guest.
Also fixes a Makefile bug in hvmloader directory.
Signed-off-by: Qing He <qing.he@intel.com>
directory pending tighter integration of table generation
into hvmloader. This patch also includes the TPM TIS SSDT
generator from Stefan Berger at IBM.
Signed-off-by: Keir Fraser <keir@xensource.com>
