mirror of
https://github.com/xen-project/xen.git
synced 2026-10-28 02:01:24 +01:00
Roger Pau Monne
cfd5232431
After some recent change the order of MTRR vs PCI initialization is
inverted. MTRR will get initialization ahead of PCI scanning and sizing of
MMIO regions. As a result when setting up MTRRs the MMIO window below 4GB
will always have the same size, and there will be no window above 4GB.
This results in malformed and incomplete MTRRs being setup.
Fix by making sure PCI is initialized ahead of MTRR, also add a comment to
notice the ordering dependency.
Fixes: 2c3dffbaa3 ('tools/hvmloader: Replace LAPIC_ID() with cpu_to_apicid[]')
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
457 lines
14 KiB
C
457 lines
14 KiB
C
/*
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* hvmloader.c: HVM bootloader.
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*
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* Leendert van Doorn, leendert@watson.ibm.com
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* Copyright (c) 2005, International Business Machines Corporation.
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*
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* Copyright (c) 2006, Keir Fraser, XenSource Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "util.h"
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#include "hypercall.h"
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#include "config.h"
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#include "pci_regs.h"
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#include "apic_regs.h"
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#include "vnuma.h"
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#include <acpi2_0.h>
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#include <xen/version.h>
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#include <xen/hvm/params.h>
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#include <xen/arch-x86/hvm/start_info.h>
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const struct hvm_start_info *hvm_start_info;
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asm (
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" .text \n"
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" .globl _start \n"
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"_start: \n"
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/* C runtime kickoff. */
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" cld \n"
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" cli \n"
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" lgdt gdt_desr \n"
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" mov $"STR(SEL_DATA32)",%ax \n"
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" mov %ax,%ds \n"
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" mov %ax,%es \n"
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" mov %ax,%fs \n"
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" mov %ax,%gs \n"
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" mov %ax,%ss \n"
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" ljmp $"STR(SEL_CODE32)",$1f \n"
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"1: movl $stack_top,%esp \n"
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" movl %esp,%ebp \n"
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/* store HVM start info ptr */
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" mov %ebx, hvm_start_info \n"
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" call main \n"
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/* Relocate real-mode trampoline to 0x0. */
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" mov $trampoline_start,%esi \n"
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" xor %edi,%edi \n"
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" mov $trampoline_end,%ecx \n"
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" sub %esi,%ecx \n"
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" rep movsb \n"
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/* Load real-mode compatible segment state (base 0x0000, limit 0xffff). */
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" mov $"STR(SEL_DATA16)",%ax \n"
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" mov %ax,%ds \n"
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" mov %ax,%es \n"
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" mov %ax,%fs \n"
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" mov %ax,%gs \n"
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" mov %ax,%ss \n"
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/* Initialise all 32-bit GPRs to zero. */
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" xor %eax,%eax \n"
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" xor %ebx,%ebx \n"
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" xor %ecx,%ecx \n"
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" xor %edx,%edx \n"
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" xor %esp,%esp \n"
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" xor %ebp,%ebp \n"
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" xor %esi,%esi \n"
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" xor %edi,%edi \n"
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/* Enter real mode, reload all segment registers and IDT. */
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" ljmp $"STR(SEL_CODE16)",$0x0\n"
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"trampoline_start: .code16 \n"
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" mov %eax,%cr0 \n"
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" ljmp $0,$1f-trampoline_start\n"
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"1: mov %ax,%ds \n"
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" mov %ax,%es \n"
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" mov %ax,%fs \n"
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" mov %ax,%gs \n"
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" mov %ax,%ss \n"
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" lidt 1f-trampoline_start \n"
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" ljmp $0xf000,$0xfff0 \n"
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"1: .word 0x3ff,0,0 \n"
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"trampoline_end: .code32 \n"
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" \n"
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"gdt_desr: \n"
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" .word gdt_end - gdt - 1 \n"
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" .long gdt \n"
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" \n"
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" .align 8 \n"
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"gdt: \n"
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" .quad 0x0000000000000000 \n"
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" .quad 0x008f9a000000ffff \n" /* Ring 0 16b code, base 0 limit 4G */
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" .quad 0x008f92000000ffff \n" /* Ring 0 16b data, base 0 limit 4G */
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" .quad 0x00cf9a000000ffff \n" /* Ring 0 32b code, base 0 limit 4G */
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" .quad 0x00cf92000000ffff \n" /* Ring 0 32b data, base 0 limit 4G */
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" .quad 0x00af9a000000ffff \n" /* Ring 0 64b code */
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"gdt_end: \n"
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" \n"
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" .bss \n"
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" .align 8 \n"
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"stack: \n"
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" .skip 0x4000 \n"
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"stack_top: \n"
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" .text \n"
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);
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unsigned long scratch_start = SCRATCH_PHYSICAL_ADDRESS;
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uint8_t ioapic_version;
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bool acpi_enabled;
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static void init_hypercalls(void)
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{
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uint32_t eax, ebx, ecx, edx;
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unsigned long i;
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char signature[13];
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xen_extraversion_t extraversion;
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uint32_t base;
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for ( base = 0x40000000; base < 0x40010000; base += 0x100 )
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{
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cpuid(base, &eax, &ebx, &ecx, &edx);
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*(uint32_t *)(signature + 0) = ebx;
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*(uint32_t *)(signature + 4) = ecx;
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*(uint32_t *)(signature + 8) = edx;
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signature[12] = '\0';
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if ( !strcmp("XenVMMXenVMM", signature) )
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break;
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}
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BUG_ON(strcmp("XenVMMXenVMM", signature) || ((eax - base) < 2));
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/* Fill in hypercall transfer pages. */
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cpuid(base + 2, &eax, &ebx, &ecx, &edx);
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for ( i = 0; i < eax; i++ )
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wrmsr(ebx, HYPERCALL_PHYSICAL_ADDRESS + (i << 12) + i);
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/* Print version information. */
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cpuid(base + 1, &eax, &ebx, &ecx, &edx);
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hypercall_xen_version(XENVER_extraversion, extraversion);
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printf("Detected Xen v%u.%u%s\n", eax >> 16, eax & 0xffff, extraversion);
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}
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/* Replace possibly erroneous memory-size CMOS fields with correct values. */
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static void cmos_write_memory_size(void)
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{
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uint32_t base_mem = 640, ext_mem, alt_mem;
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alt_mem = ext_mem = hvm_info->low_mem_pgend << PAGE_SHIFT;
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ext_mem = (ext_mem > 0x0100000) ? (ext_mem - 0x0100000) >> 10 : 0;
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if ( ext_mem > 0xffff )
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ext_mem = 0xffff;
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alt_mem = (alt_mem > 0x1000000) ? (alt_mem - 0x1000000) >> 16 : 0;
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/* All BIOSes: conventional memory (CMOS *always* reports 640kB). */
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cmos_outb(0x15, (uint8_t)(base_mem >> 0));
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cmos_outb(0x16, (uint8_t)(base_mem >> 8));
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/* All BIOSes: extended memory (1kB chunks above 1MB). */
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cmos_outb(0x17, (uint8_t)( ext_mem >> 0));
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cmos_outb(0x18, (uint8_t)( ext_mem >> 8));
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cmos_outb(0x30, (uint8_t)( ext_mem >> 0));
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cmos_outb(0x31, (uint8_t)( ext_mem >> 8));
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/* Some BIOSes: alternative extended memory (64kB chunks above 16MB). */
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cmos_outb(0x34, (uint8_t)( alt_mem >> 0));
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cmos_outb(0x35, (uint8_t)( alt_mem >> 8));
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}
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/*
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* Set up an empty TSS area for virtual 8086 mode to use. Its content is
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* going to be managed by Xen, but zero fill it just in case.
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*/
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static void init_vm86_tss(void)
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{
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/*
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* Have the TSS cover the ISA port range, which makes it
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* - 104 bytes base structure
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* - 32 bytes interrupt redirection bitmap
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* - 128 bytes I/O bitmap
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* - one trailing byte
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* or a total of to 265 bytes. As it needs to be a multiple of the requested
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* alignment, this ends up requiring 384 bytes.
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*/
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#define TSS_SIZE (3 * 128)
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void *tss;
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tss = mem_alloc(TSS_SIZE, 128);
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memset(tss, 0, TSS_SIZE);
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hvm_param_set(HVM_PARAM_VM86_TSS_SIZED,
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((uint64_t)TSS_SIZE << 32) | virt_to_phys(tss));
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printf("vm86 TSS at %08lx\n", virt_to_phys(tss));
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#undef TSS_SIZE
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}
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static void apic_setup(void)
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{
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/*
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* This would the The Right Thing To Do (tm), if only qemu negotiated
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* with Xen where the IO-APIC actually sits (which is currently hard
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* coded in Xen and can't be controlled externally). Uncomment this code
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* once that changed.
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ioapic_base_address |= (pci_readb(PCI_ISA_DEVFN, 0x80) & 0x3f) << 10;
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*/
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ioapic_version = ioapic_read(0x01) & 0xff;
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/* Set the IOAPIC ID to the static value used in the MP/ACPI tables. */
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ioapic_write(0x00, IOAPIC_ID);
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/* NMIs are delivered direct to the BSP. */
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lapic_write(APIC_SPIV, APIC_SPIV_APIC_ENABLED | 0xFF);
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lapic_write(APIC_LVT0, (APIC_MODE_EXTINT << 8) | APIC_LVT_MASKED);
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lapic_write(APIC_LVT1, APIC_MODE_NMI << 8);
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/* 8259A ExtInts are delivered through IOAPIC pin 0 (Virtual Wire Mode). */
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ioapic_write(0x10, APIC_DM_EXTINT);
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ioapic_write(0x11, SET_APIC_ID(cpu_to_apicid[0]));
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}
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struct bios_info {
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const char *key;
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const struct bios_config *bios;
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} bios_configs[] = {
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#ifdef ENABLE_ROMBIOS
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{ "rombios", &rombios_config, },
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#endif
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{ "seabios", &seabios_config, },
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{ "ovmf", &ovmf_config, },
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{ NULL, NULL }
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};
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static const struct bios_config *detect_bios(void)
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{
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const struct bios_info *b;
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const char *bios;
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bios = xenstore_read("hvmloader/bios", "rombios");
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for ( b = &bios_configs[0]; b->key != NULL; b++ )
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if ( !strcmp(bios, b->key) )
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return b->bios;
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printf("Unknown BIOS %s, no ROM image found\n", bios);
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BUG();
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return NULL;
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}
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static void acpi_enable_sci(void)
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{
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uint8_t pm1a_cnt_val;
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#define PIIX4_SMI_CMD_IOPORT 0xb2
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#define PIIX4_ACPI_ENABLE 0xf1
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/*
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* PIIX4 emulation in QEMU has SCI_EN=0 by default. We have no legacy
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* SMM implementation, so give ACPI control to the OSPM immediately.
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*/
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pm1a_cnt_val = inb(ACPI_PM1A_CNT_BLK_ADDRESS_V1);
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if ( !(pm1a_cnt_val & ACPI_PM1C_SCI_EN) )
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outb(PIIX4_SMI_CMD_IOPORT, PIIX4_ACPI_ENABLE);
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pm1a_cnt_val = inb(ACPI_PM1A_CNT_BLK_ADDRESS_V1);
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BUG_ON(!(pm1a_cnt_val & ACPI_PM1C_SCI_EN));
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}
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const struct hvm_modlist_entry *get_module_entry(
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const struct hvm_start_info *info,
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const char *name)
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{
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const struct hvm_modlist_entry *modlist =
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(struct hvm_modlist_entry *)(uintptr_t)info->modlist_paddr;
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unsigned int i;
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if ( !modlist ||
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info->modlist_paddr > UINTPTR_MAX ||
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(UINTPTR_MAX - (uintptr_t)info->modlist_paddr) / sizeof(*modlist)
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< info->nr_modules )
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return NULL;
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for ( i = 0; i < info->nr_modules; i++ )
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{
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char *module_name = (char*)(uintptr_t)modlist[i].cmdline_paddr;
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/* Skip if the module or its cmdline is missing. */
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if ( !module_name || !modlist[i].paddr )
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continue;
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/* Skip if the cmdline cannot be read. */
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if ( modlist[i].cmdline_paddr > UINTPTR_MAX ||
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(modlist[i].cmdline_paddr + strlen(name)) > UINTPTR_MAX )
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continue;
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if ( !strcmp(name, module_name) )
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{
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if ( modlist[i].paddr > UINTPTR_MAX ||
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modlist[i].size > UINTPTR_MAX ||
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(modlist[i].paddr + modlist[i].size - 1) > UINTPTR_MAX )
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{
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printf("Cannot load \"%s\" from 0x"PRIllx" (0x"PRIllx")\n",
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name, PRIllx_arg(modlist[i].paddr),
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PRIllx_arg(modlist[i].size));
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BUG();
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}
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return &modlist[i];
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}
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}
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return NULL;
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}
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int main(void)
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{
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const struct bios_config *bios;
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const struct hvm_modlist_entry *bios_module;
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/* Initialise hypercall stubs with RET, rendering them no-ops. */
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memset((void *)HYPERCALL_PHYSICAL_ADDRESS, 0xc3 /* RET */, PAGE_SIZE);
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printf("HVM Loader\n");
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BUG_ON(hvm_start_info->magic != XEN_HVM_START_MAGIC_VALUE);
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init_hypercalls();
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memory_map_setup();
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xenbus_setup();
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bios = detect_bios();
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printf("System requested %s\n", bios->name);
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printf("CPU speed is %u MHz\n", get_cpu_mhz());
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/*
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* PCI setup must be done before SMP initialization, as the later also does
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* the MTRR setup and so the size of the PCI MMIO windows must be known at
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* that point.
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*/
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pci_setup();
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smp_initialise();
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apic_setup();
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perform_tests();
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if ( bios->bios_info_setup )
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bios->bios_info_setup();
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if ( bios->create_smbios_tables )
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{
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printf("Writing SMBIOS tables ...\n");
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bios->create_smbios_tables();
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}
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printf("Loading %s ...\n", bios->name);
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bios_module = get_module_entry(hvm_start_info, "firmware");
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if ( bios_module )
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{
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uint32_t paddr = bios_module->paddr;
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bios->bios_load(bios, (void *)paddr, bios_module->size, NULL);
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}
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#ifdef ENABLE_ROMBIOS
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else if ( bios == &rombios_config )
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{
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const struct hvm_modlist_entry *ipxe;
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uint32_t paddr = 0;
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ipxe = get_module_entry(hvm_start_info, "ipxe");
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if ( ipxe )
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paddr = ipxe->paddr;
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bios->bios_load(bios, NULL, 0, (void *)paddr);
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}
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#endif
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else
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{
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/*
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* If there is no BIOS module supplied and if there is no embeded BIOS
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* image, then we failed. Only rombios might have an embedded bios blob.
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*/
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printf("no BIOS ROM image found\n");
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BUG();
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}
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if ( (hvm_info->nr_vcpus > 1) || hvm_info->apic_mode )
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{
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if ( bios->create_mp_tables )
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bios->create_mp_tables();
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if ( bios->create_pir_tables )
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bios->create_pir_tables();
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}
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if ( bios->load_roms )
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bios->load_roms();
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acpi_enabled = !strncmp(xenstore_read("platform/acpi", "1"), "1", 1);
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if ( acpi_enabled )
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{
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init_vnuma_info();
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if ( bios->acpi_build_tables )
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{
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printf("Loading ACPI ...\n");
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bios->acpi_build_tables();
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}
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acpi_enable_sci();
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hvm_param_set(HVM_PARAM_ACPI_IOPORTS_LOCATION, 1);
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}
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init_vm86_tss();
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cmos_write_memory_size();
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printf("BIOS map:\n");
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if ( SCRATCH_PHYSICAL_ADDRESS != scratch_start )
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printf(" %05x-%05lx: Scratch space\n",
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SCRATCH_PHYSICAL_ADDRESS, scratch_start);
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printf(" %05x-%05x: Main BIOS\n",
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bios->bios_address,
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bios->bios_address + bios->image_size - 1);
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if ( bios->e820_setup )
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bios->e820_setup();
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if ( bios->bios_info_finish )
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bios->bios_info_finish();
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xenbus_shutdown();
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printf("Invoking %s ...\n", bios->name);
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return 0;
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}
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/*
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* Local variables:
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* mode: C
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* c-file-style: "BSD"
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* c-basic-offset: 4
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* tab-width: 4
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* indent-tabs-mode: nil
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* End:
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*/
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