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https://github.com/xen-project/xen.git
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Jan Beulich
ea187c0b7a
This reverts commitc22bd567ce. While its description is correct from an abstract or real hardware pov, the range is special inside HVM guests. The range being UC in particular gets in the way of OVMF, which places itself at [FFE00000,FFFFFFFF]. While this is benign to epte_get_entry_emt() as long as the IOMMU isn't enabled for a guest, it becomes a very noticable problem otherwise: It takes about half a minute for OVMF to decompress itself into its designated address range. And even beyond OVMF there's no reason to have e.g. the ACPI memory range marked UC. Fixes:c22bd567ce("hvmloader: PA range 0xfc000000-0xffffffff should be UC") Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Roger Pau Monné <roger.pau@citrix.com> Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
145 lines
4.2 KiB
C
145 lines
4.2 KiB
C
/*
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* cacheattr.c: MTRR and PAT initialisation.
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*
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* Copyright (c) 2008, Citrix Systems, Inc.
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*
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* Authors:
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* Keir Fraser <keir@xen.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "util.h"
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#include "config.h"
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#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
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#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
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#define MSR_MTRRcap 0x00fe
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#define MSR_MTRRfix64K_00000 0x0250
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#define MSR_MTRRfix16K_80000 0x0258
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#define MSR_MTRRfix16K_A0000 0x0259
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#define MSR_MTRRfix4K_C0000 0x0268
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#define MSR_MTRRfix4K_C8000 0x0269
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#define MSR_MTRRfix4K_D0000 0x026a
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#define MSR_MTRRfix4K_D8000 0x026b
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#define MSR_MTRRfix4K_E0000 0x026c
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#define MSR_MTRRfix4K_E8000 0x026d
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#define MSR_MTRRfix4K_F0000 0x026e
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#define MSR_MTRRfix4K_F8000 0x026f
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#define MSR_PAT 0x0277
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#define MSR_MTRRdefType 0x02ff
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unsigned int cpu_phys_addr(void)
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{
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uint32_t eax, ebx, ecx, edx;
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unsigned int phys_bits = 36;
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/* Find the physical address size for this CPU. */
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cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
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if ( eax >= 0x80000008 )
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{
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cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
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phys_bits = (uint8_t)eax;
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}
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return phys_bits;
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}
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void cacheattr_init(void)
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{
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uint32_t eax, ebx, ecx, edx;
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uint64_t mtrr_cap, mtrr_def, content, addr_mask;
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unsigned int i, nr_var_ranges, phys_bits;
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/* Does the CPU support architectural MTRRs? */
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cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
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if ( !(edx & (1u << 12)) )
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return;
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phys_bits = cpu_phys_addr();
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printf("%u-bit phys ... ", phys_bits);
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addr_mask = ((1ull << phys_bits) - 1) & ~((1ull << 12) - 1);
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mtrr_cap = rdmsr(MSR_MTRRcap);
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mtrr_def = (1u << 11) | 6; /* E, default type WB */
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/* Fixed-range MTRRs supported? */
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if ( mtrr_cap & (1u << 8) )
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{
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/* 0x00000-0x9ffff: Write Back (WB) */
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content = 0x0606060606060606ull;
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wrmsr(MSR_MTRRfix64K_00000, content);
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wrmsr(MSR_MTRRfix16K_80000, content);
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/* 0xa0000-0xbffff: Write Combining (WC) */
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if ( mtrr_cap & (1u << 10) ) /* WC supported? */
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content = 0x0101010101010101ull;
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wrmsr(MSR_MTRRfix16K_A0000, content);
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/* 0xc0000-0xfffff: Write Back (WB) */
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content = 0x0606060606060606ull;
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for ( i = 0; i < 8; i++ )
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wrmsr(MSR_MTRRfix4K_C0000 + i, content);
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mtrr_def |= 1u << 10; /* FE */
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printf("fixed MTRRs ... ");
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}
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/* Variable-range MTRRs supported? */
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nr_var_ranges = (uint8_t)mtrr_cap;
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if ( nr_var_ranges != 0 )
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{
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uint64_t base = pci_mem_start, size;
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for ( i = 0; (base != pci_mem_end) && (i < nr_var_ranges); i++ )
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{
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size = PAGE_SIZE;
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while ( !(base & size) )
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size <<= 1;
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while ( ((base + size) < base) || ((base + size) > pci_mem_end) )
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size >>= 1;
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wrmsr(MSR_MTRRphysBase(i), base);
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wrmsr(MSR_MTRRphysMask(i), (~(size - 1) & addr_mask) | (1u << 11));
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base += size;
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}
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for ( base = pci_hi_mem_start;
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(base != pci_hi_mem_end) && (i < nr_var_ranges); i++ )
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{
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size = PAGE_SIZE;
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while ( !(base & size) )
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size <<= 1;
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while ( (base + size < base) || (base + size > pci_hi_mem_end) )
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size >>= 1;
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wrmsr(MSR_MTRRphysBase(i), base);
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wrmsr(MSR_MTRRphysMask(i), (~(size - 1) & addr_mask) | (1u << 11));
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base += size;
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}
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printf("var MTRRs [%d/%d] ... ", i, nr_var_ranges);
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}
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wrmsr(MSR_MTRRdefType, mtrr_def);
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}
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/*
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* Local variables:
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* mode: C
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* c-file-style: "BSD"
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* c-basic-offset: 4
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* tab-width: 4
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* indent-tabs-mode: nil
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* End:
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*/
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