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Andrew Cooper
d297b56682
Intel specifies IBRS/IBPB (combined, in a single bit) and STIBP as a separate bit. AMD specifies IBPB alone in a 3rd bit. AMD's IBPB is a subset of Intel's combined IBRS/IBPB. For performance reasons, administrators might wish to express "IBPB only" even on Intel hardware, so we allow the AMD bit to be used for this purpose. The behaviour of STIBP is more complicated. It is our current understanding that STIBP will be advertised on HT-capable hardware irrespective of whether HT is enabled, but not advertised on HT-incapable hardware. However, for ease of virtualisation, STIBP's functionality is ignored rather than reserved by microcode/hardware on HT-incapable hardware. For guest safety, we treat STIBP as special, always override the toolstack choice, and always advertise STIBP if IBRS is available. This removes the corner case where STIBP is not advertised, but the guest is running on HT-capable hardware where it does matter. Finally as a bugfix, update the libxc CPUID logic to understand the e8b feature leaf, which has the side effect of also offering CLZERO to guests on applicable hardware. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Wei Liu <wei.liu2@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com>