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kaf24@firebug.cl.cam.ac.uk
11d666ab5e
Xserver will scan pci and the cirrus VGA driver will register mmio each time, cause mmio array out of space. Signed-off-by: Xiaofeng Ling <xiaofeng.ling@intel.com>
506 lines
14 KiB
C
506 lines
14 KiB
C
/*
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* virtual page mapping and translated block handling
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "config.h"
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#ifdef _WIN32
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#include <windows.h>
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#else
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#include <sys/types.h>
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#include <sys/mman.h>
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#endif
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include <string.h>
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#include <errno.h>
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#include <unistd.h>
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#include <inttypes.h>
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#include "cpu.h"
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#include "exec-all.h"
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//#define DEBUG_TB_INVALIDATE
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//#define DEBUG_FLUSH
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//#define DEBUG_TLB
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/* make various TB consistency checks */
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//#define DEBUG_TB_CHECK
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//#define DEBUG_TLB_CHECK
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/* threshold to flush the translated code buffer */
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#define CODE_GEN_BUFFER_MAX_SIZE (CODE_GEN_BUFFER_SIZE - CODE_GEN_MAX_SIZE)
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#define SMC_BITMAP_USE_THRESHOLD 10
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#define MMAP_AREA_START 0x00000000
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#define MMAP_AREA_END 0xa8000000
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TranslationBlock tbs[CODE_GEN_MAX_BLOCKS];
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TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
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TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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int nb_tbs;
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/* any access to the tbs or the page table must use this lock */
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spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
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uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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uint8_t *code_gen_ptr;
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int phys_ram_size;
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int phys_ram_fd;
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uint8_t *phys_ram_base;
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uint8_t *phys_ram_dirty;
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typedef struct PageDesc {
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/* list of TBs intersecting this ram page */
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TranslationBlock *first_tb;
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/* in order to optimize self modifying code, we count the number
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of lookups we do to a given page to use a bitmap */
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unsigned int code_write_count;
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uint8_t *code_bitmap;
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#if defined(CONFIG_USER_ONLY)
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unsigned long flags;
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#endif
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} PageDesc;
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typedef struct PhysPageDesc {
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/* offset in host memory of the page + io_index in the low 12 bits */
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unsigned long phys_offset;
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} PhysPageDesc;
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typedef struct VirtPageDesc {
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/* physical address of code page. It is valid only if 'valid_tag'
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matches 'virt_valid_tag' */
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target_ulong phys_addr;
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unsigned int valid_tag;
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#if !defined(CONFIG_SOFTMMU)
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/* original page access rights. It is valid only if 'valid_tag'
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matches 'virt_valid_tag' */
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unsigned int prot;
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#endif
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} VirtPageDesc;
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#define L2_BITS 10
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#define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS)
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#define L1_SIZE (1 << L1_BITS)
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#define L2_SIZE (1 << L2_BITS)
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unsigned long qemu_real_host_page_size;
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unsigned long qemu_host_page_bits;
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unsigned long qemu_host_page_size;
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unsigned long qemu_host_page_mask;
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/* io memory support */
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CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
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CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
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void *io_mem_opaque[IO_MEM_NB_ENTRIES];
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static int io_mem_nb = 1;
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/* log support */
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char *logfilename = "/tmp/qemu.log";
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FILE *logfile;
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int loglevel;
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void cpu_exec_init(void)
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{
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/* alloc dirty bits array */
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phys_ram_dirty = qemu_malloc(phys_ram_size >> TARGET_PAGE_BITS);
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}
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/* enable or disable low levels log */
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void cpu_set_log(int log_flags)
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{
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loglevel = log_flags;
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if (!logfile) {
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logfile = fopen(logfilename, "w");
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if (!logfile) {
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perror(logfilename);
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_exit(1);
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}
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#if !defined(CONFIG_SOFTMMU)
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/* must avoid mmap() usage of glibc by setting a buffer "by hand" */
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{
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static uint8_t logfile_buf[4096];
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setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
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}
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#else
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setvbuf(logfile, NULL, _IOLBF, 0);
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#endif
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/*
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stdout = logfile;
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stderr = logfile;
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*/
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}
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}
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void cpu_set_log_filename(const char *filename)
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{
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logfilename = strdup(filename);
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}
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/* mask must never be zero, except for A20 change call */
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void cpu_interrupt(CPUState *env, int mask)
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{
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env->interrupt_request |= mask;
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}
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void cpu_reset_interrupt(CPUState *env, int mask)
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{
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env->interrupt_request &= ~mask;
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}
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CPULogItem cpu_log_items[] = {
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{ CPU_LOG_TB_OUT_ASM, "out_asm",
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"show generated host assembly code for each compiled TB" },
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{ CPU_LOG_TB_IN_ASM, "in_asm",
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"show target assembly code for each compiled TB" },
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{ CPU_LOG_TB_OP, "op",
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"show micro ops for each compiled TB (only usable if 'in_asm' used)" },
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#ifdef TARGET_I386
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{ CPU_LOG_TB_OP_OPT, "op_opt",
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"show micro ops after optimization for each compiled TB" },
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#endif
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{ CPU_LOG_INT, "int",
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"show interrupts/exceptions in short format" },
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{ CPU_LOG_EXEC, "exec",
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"show trace before each executed TB (lots of logs)" },
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{ CPU_LOG_TB_CPU, "cpu",
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"show CPU state before bloc translation" },
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#ifdef TARGET_I386
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{ CPU_LOG_PCALL, "pcall",
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"show protected mode far calls/returns/exceptions" },
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#endif
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#ifdef DEBUG_IOPORT
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{ CPU_LOG_IOPORT, "ioport",
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"show all i/o ports accesses" },
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#endif
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{ 0, NULL, NULL },
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};
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static int cmp1(const char *s1, int n, const char *s2)
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{
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if (strlen(s2) != n)
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return 0;
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return memcmp(s1, s2, n) == 0;
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}
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/* takes a comma separated list of log masks. Return 0 if error. */
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int cpu_str_to_log_mask(const char *str)
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{
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CPULogItem *item;
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int mask;
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const char *p, *p1;
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p = str;
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mask = 0;
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for(;;) {
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p1 = strchr(p, ',');
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if (!p1)
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p1 = p + strlen(p);
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if(cmp1(p,p1-p,"all")) {
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for(item = cpu_log_items; item->mask != 0; item++) {
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mask |= item->mask;
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}
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} else {
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for(item = cpu_log_items; item->mask != 0; item++) {
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if (cmp1(p, p1 - p, item->name))
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goto found;
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}
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return 0;
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}
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found:
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mask |= item->mask;
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if (*p1 != ',')
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break;
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p = p1 + 1;
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}
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return mask;
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}
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void cpu_abort(CPUState *env, const char *fmt, ...)
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{
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va_list ap;
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va_start(ap, fmt);
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fprintf(stderr, "qemu: fatal: ");
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vfprintf(stderr, fmt, ap);
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fprintf(stderr, "\n");
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va_end(ap);
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abort();
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}
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/* XXX: Simple implementation. Fix later */
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#define MAX_MMIO 32
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struct mmio_space {
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target_phys_addr_t start;
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unsigned long size;
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unsigned long io_index;
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} mmio[MAX_MMIO];
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unsigned long mmio_cnt;
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/* register physical memory. 'size' must be a multiple of the target
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page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
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io memory page */
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void cpu_register_physical_memory(target_phys_addr_t start_addr,
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unsigned long size,
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unsigned long phys_offset)
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{
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int i;
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for (i = 0; i < mmio_cnt; i++) {
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if(mmio[i].start == start_addr) {
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mmio[i].io_index = phys_offset;
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mmio[i].size = size;
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return;
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}
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}
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if (mmio_cnt == MAX_MMIO) {
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fprintf(logfile, "too many mmio regions\n");
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exit(-1);
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}
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mmio[mmio_cnt].io_index = phys_offset;
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mmio[mmio_cnt].start = start_addr;
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mmio[mmio_cnt++].size = size;
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}
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/* mem_read and mem_write are arrays of functions containing the
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function to access byte (index 0), word (index 1) and dword (index
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2). All functions must be supplied. If io_index is non zero, the
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corresponding io zone is modified. If it is zero, a new io zone is
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allocated. The return value can be used with
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cpu_register_physical_memory(). (-1) is returned if error. */
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int cpu_register_io_memory(int io_index,
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CPUReadMemoryFunc **mem_read,
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CPUWriteMemoryFunc **mem_write,
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void *opaque)
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{
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int i;
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if (io_index <= 0) {
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if (io_index >= IO_MEM_NB_ENTRIES)
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return -1;
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io_index = io_mem_nb++;
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} else {
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if (io_index >= IO_MEM_NB_ENTRIES)
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return -1;
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}
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for(i = 0;i < 3; i++) {
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io_mem_read[io_index][i] = mem_read[i];
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io_mem_write[io_index][i] = mem_write[i];
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}
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io_mem_opaque[io_index] = opaque;
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return io_index << IO_MEM_SHIFT;
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}
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CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index)
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{
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return io_mem_write[io_index >> IO_MEM_SHIFT];
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}
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CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index)
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{
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return io_mem_read[io_index >> IO_MEM_SHIFT];
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}
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/* physical memory access (slow version, mainly for debug) */
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#if defined(CONFIG_USER_ONLY)
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void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
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int len, int is_write)
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{
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int l, flags;
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target_ulong page;
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while (len > 0) {
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page = addr & TARGET_PAGE_MASK;
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l = (page + TARGET_PAGE_SIZE) - addr;
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if (l > len)
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l = len;
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flags = page_get_flags(page);
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if (!(flags & PAGE_VALID))
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return;
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if (is_write) {
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if (!(flags & PAGE_WRITE))
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return;
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memcpy((uint8_t *)addr, buf, len);
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} else {
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if (!(flags & PAGE_READ))
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return;
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memcpy(buf, (uint8_t *)addr, len);
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}
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len -= l;
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buf += l;
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addr += l;
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}
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}
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#else
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int iomem_index(target_phys_addr_t addr)
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{
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int i;
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for (i = 0; i < mmio_cnt; i++) {
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unsigned long start, end;
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start = mmio[i].start;
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end = mmio[i].start + mmio[i].size;
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if ((addr >= start) && (addr <= end)){
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return (mmio[i].io_index >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
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}
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}
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return 0;
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}
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#ifdef __ia64__
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/* IA64 has seperate I/D cache, with coherence maintained by DMA controller.
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* So to emulate right behavior that guest OS is assumed, we need to flush
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* I/D cache here.
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*/
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static void sync_icache(unsigned long address, int len)
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{
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int l;
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for(l = 0; l < (len + 32); l += 32)
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__ia64_fc(address + l);
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ia64_sync_i();
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ia64_srlz_i();
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}
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#endif
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void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
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int len, int is_write)
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{
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int l, io_index;
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uint8_t *ptr;
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uint32_t val;
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target_phys_addr_t page;
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unsigned long pd;
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while (len > 0) {
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page = addr & TARGET_PAGE_MASK;
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l = (page + TARGET_PAGE_SIZE) - addr;
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if (l > len)
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l = len;
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pd = page;
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io_index = iomem_index(page);
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if (is_write) {
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if (io_index) {
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if (l >= 4 && ((addr & 3) == 0)) {
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/* 32 bit read access */
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val = ldl_raw(buf);
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io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
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l = 4;
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} else if (l >= 2 && ((addr & 1) == 0)) {
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/* 16 bit read access */
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val = lduw_raw(buf);
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io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val);
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l = 2;
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} else {
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/* 8 bit access */
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val = ldub_raw(buf);
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io_mem_write[io_index][0](io_mem_opaque[io_index], addr, val);
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l = 1;
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}
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} else {
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unsigned long addr1;
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addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
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/* RAM case */
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ptr = phys_ram_base + addr1;
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memcpy(ptr, buf, l);
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#ifdef __ia64__
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sync_icache((unsigned long)ptr,l);
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#endif
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}
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} else {
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if (io_index) {
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if (l >= 4 && ((addr & 3) == 0)) {
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/* 32 bit read access */
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val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
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stl_raw(buf, val);
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l = 4;
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} else if (l >= 2 && ((addr & 1) == 0)) {
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/* 16 bit read access */
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val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr);
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stw_raw(buf, val);
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l = 2;
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} else {
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/* 8 bit access */
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val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr);
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stb_raw(buf, val);
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l = 1;
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}
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} else {
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/* RAM case */
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ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) +
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(addr & ~TARGET_PAGE_MASK);
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memcpy(buf, ptr, l);
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}
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}
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len -= l;
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buf += l;
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addr += l;
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}
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}
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#endif
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/* virtual memory access for debug */
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int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
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uint8_t *buf, int len, int is_write)
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{
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int l;
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target_ulong page, phys_addr;
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while (len > 0) {
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page = addr & TARGET_PAGE_MASK;
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phys_addr = cpu_get_phys_page_debug(env, page);
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/* if no physical page mapped, return an error */
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if (phys_addr == -1)
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return -1;
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l = (page + TARGET_PAGE_SIZE) - addr;
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if (l > len)
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l = len;
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cpu_physical_memory_rw(phys_addr + (addr & ~TARGET_PAGE_MASK),
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buf, l, is_write);
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len -= l;
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buf += l;
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addr += l;
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}
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return 0;
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}
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void cpu_physical_memory_reset_dirty(target_ulong start, target_ulong end)
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{
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uint8_t *p;
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int len;
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if ((len = (end - start)) <= 0)
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return;
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p = phys_ram_dirty + (start >> TARGET_PAGE_BITS);
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len = len >> TARGET_PAGE_BITS;
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while (len > 0)
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p[--len] &= ~VGA_DIRTY_FLAG;
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return;
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}
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