mirror of
https://github.com/xen-project/xen.git
synced 2026-10-28 02:01:24 +01:00
Oleksii Kurochko
13684f539e
Set up fixmap mappings and the L0 page table for fixmap support.
Modify the PTEs (xen_fixmap[]) directly in arch_pmap_map() instead
of using set_fixmap() which is expected to be implemented using
map_pages_to_xen(), which, in turn, is expected to use
arch_pmap_map() during early boot, resulting in a loop.
Define new macros in riscv/config.h for calculating
the FIXMAP_BASE address, including BOOT_FDT_VIRT_{START, SIZE},
XEN_VIRT_SIZE, and XEN_VIRT_END.
Update the check for Xen size in riscv/xen.lds.S to use
XEN_VIRT_SIZE instead of a hardcoded constant.
Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
100 lines
2.6 KiB
C
100 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _ASM_RISCV_PAGE_H
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#define _ASM_RISCV_PAGE_H
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#ifndef __ASSEMBLY__
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#include <xen/const.h>
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#include <xen/bug.h>
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#include <xen/types.h>
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#include <asm/atomic.h>
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#include <asm/mm.h>
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#include <asm/page-bits.h>
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#define VPN_MASK (PAGETABLE_ENTRIES - 1UL)
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#define XEN_PT_LEVEL_ORDER(lvl) ((lvl) * PAGETABLE_ORDER)
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#define XEN_PT_LEVEL_SHIFT(lvl) (XEN_PT_LEVEL_ORDER(lvl) + PAGE_SHIFT)
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#define XEN_PT_LEVEL_SIZE(lvl) (_AT(paddr_t, 1) << XEN_PT_LEVEL_SHIFT(lvl))
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#define XEN_PT_LEVEL_MAP_MASK(lvl) (~(XEN_PT_LEVEL_SIZE(lvl) - 1))
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#define XEN_PT_LEVEL_MASK(lvl) (VPN_MASK << XEN_PT_LEVEL_SHIFT(lvl))
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#define PTE_VALID BIT(0, UL)
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#define PTE_READABLE BIT(1, UL)
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#define PTE_WRITABLE BIT(2, UL)
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#define PTE_EXECUTABLE BIT(3, UL)
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#define PTE_USER BIT(4, UL)
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#define PTE_GLOBAL BIT(5, UL)
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#define PTE_ACCESSED BIT(6, UL)
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#define PTE_DIRTY BIT(7, UL)
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#define PTE_RSW (BIT(8, UL) | BIT(9, UL))
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#define PTE_LEAF_DEFAULT (PTE_VALID | PTE_READABLE | PTE_WRITABLE)
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#define PTE_TABLE (PTE_VALID)
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#define PAGE_HYPERVISOR_RW (PTE_VALID | PTE_READABLE | PTE_WRITABLE)
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#define PAGE_HYPERVISOR PAGE_HYPERVISOR_RW
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/* Calculate the offsets into the pagetables for a given VA */
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#define pt_linear_offset(lvl, va) ((va) >> XEN_PT_LEVEL_SHIFT(lvl))
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#define pt_index(lvl, va) (pt_linear_offset((lvl), (va)) & VPN_MASK)
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/* Page Table entry */
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typedef struct {
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#ifdef CONFIG_RISCV_64
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uint64_t pte;
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#else
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uint32_t pte;
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#endif
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} pte_t;
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static inline pte_t paddr_to_pte(paddr_t paddr,
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unsigned int permissions)
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{
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return (pte_t) { .pte = (paddr_to_pfn(paddr) << PTE_PPN_SHIFT) | permissions };
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}
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static inline paddr_t pte_to_paddr(pte_t pte)
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{
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return pfn_to_paddr(pte.pte >> PTE_PPN_SHIFT);
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}
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static inline bool pte_is_valid(pte_t p)
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{
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return p.pte & PTE_VALID;
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}
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static inline void invalidate_icache(void)
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{
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BUG_ON("unimplemented");
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}
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#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
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#define copy_page(dp, sp) memcpy(dp, sp, PAGE_SIZE)
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/* TODO: Flush the dcache for an entire page. */
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static inline void flush_page_to_ram(unsigned long mfn, bool sync_icache)
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{
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BUG_ON("unimplemented");
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}
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/* Write a pagetable entry. */
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static inline void write_pte(pte_t *p, pte_t pte)
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{
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write_atomic(p, pte);
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}
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/* Read a pagetable entry. */
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static inline pte_t read_pte(const pte_t *p)
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{
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return read_atomic(p);
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}
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_RISCV_PAGE_H */
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