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https://github.com/xen-project/xen.git
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Oleksii Kurochko
2addc9f051
H provides additional instructions and CSRs that control the new stage of
address translation and support hosting a guest OS in virtual S-mode
(VS-mode).
According to the Unprivileged Architecture (version 20240411) specification:
```
Table 74 summarizes the standardized extension names. The table also defines
the canonical order in which extension names must appear in the name string,
with top-to-bottom in table indicating first-to-last in the name string, e.g.,
RV32IMACV is legal, whereas RV32IMAVC is not.
```
According to Table 74, the h extension is placed last in the one-letter
extensions name part of the ISA string.
`h` is a standalone extension based on the patch [1] but it wasn't so
before.
As the minimal supported GCC version to build Xen for RISC-V is 12.2.0,
and for that version, h is still considered a prefix for the hypervisor
extension but the name of hypervisor extension must be more then 1 letter
extension, a workaround ( with using `hh` as an H extension name ) is
implemented as otherwise the following compilation error will occur:
error: '-march=rv64gc_h_zbb_zihintpause': name of hypervisor extension
must be more than 1 letter
After GCC version 13.1.0, the commit [1] introducing H extension support
allows us to drop the workaround with `hh` as hypervisor extension name
and use only one h in -march.
[1] https://github.com/gcc-mirror/gcc/commit/0cd11d301013af50a3fae0694c909952e94e20d5#diff-d6f7db0db31bfb339b01bec450f1b905381eb4730cc5ab2b2794971e34647d64R148
Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
21 lines
807 B
Plaintext
21 lines
807 B
Plaintext
System requirements
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===================
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The following extensions are expected to be supported by a system on which
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Xen is run:
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- H:
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Provides additional instructions and CSRs that control the new stage of
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address translation and support hosting a guest OS in virtual S-mode
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(VS-mode).
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- Zbb:
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RISC-V doesn't have a CLZ instruction in the base ISA.
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As a consequence, __builtin_ffs() emits a library call to ffs() on GCC,
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or a de Bruijn sequence on Clang.
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Zbb extension adds a CLZ instruction, after which __builtin_ffs() emits
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a very simple sequence.
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The similar issue occurs with other __builtin_<bitop>, so it is needed to
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provide a generic version of bitops in RISC-V bitops.h
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- Zihintpause:
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On a system that doesn't have this extension, cpu_relax() should be
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implemented properly.
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