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Stewart Hildebrand
a3c8fb450a
Introduce a handler for the PCI status register, with ability to mask the capabilities bit. The status register contains RsvdZ bits, read-only bits, and write-1-to-clear bits. Additionally, we use RsvdP to mask the capabilities bit. Introduce bitmasks to handle these in vPCI. If a bit in the bitmask is set, then the special meaning applies: ro_mask: read normal, guest write ignore (preserve on write to hardware) rw1c_mask: read normal, write 1 to clear rsvdp_mask: read as zero, guest write ignore (preserve on write to hardware) rsvdz_mask: read as zero, guest write ignore (write zero to hardware) The RO/RW1C/RsvdP/RsvdZ naming and definitions were borrowed from the PCI Express Base 6.1 specification. RsvdP/RsvdZ bits help Xen enforce our view of the world. Xen preserves the value of read-only bits on write to hardware, discarding the guests write value. This is done in case hardware wrongly implements R/O bits as R/W. The mask_cap_list flag will be set in a follow-on change. Signed-off-by: Stewart Hildebrand <stewart.hildebrand@amd.com> Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>