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Luca Fancellu
d81133d45d
On the Cortex A53, when executing in AArch64 state, a load or store instruction which uses the result of an ADRP instruction as a base register, or which uses a base register written by an instruction immediately after an ADRP to the same register, might access an incorrect address. The workaround is to enable the linker flag --fix-cortex-a53-843419 if present, to check and fix the affected sequence. Otherwise print a warning that Xen may be susceptible to this errata Signed-off-by: Luca Fancellu <luca.fancellu@arm.com> Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>