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Luca Fancellu
d81133d45d
On the Cortex A53, when executing in AArch64 state, a load or store instruction which uses the result of an ADRP instruction as a base register, or which uses a base register written by an instruction immediately after an ADRP to the same register, might access an incorrect address. The workaround is to enable the linker flag --fix-cortex-a53-843419 if present, to check and fix the affected sequence. Otherwise print a warning that Xen may be susceptible to this errata Signed-off-by: Luca Fancellu <luca.fancellu@arm.com> Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
62 lines
3.6 KiB
Plaintext
62 lines
3.6 KiB
Plaintext
Silicon Errata and Software Workarounds
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=======================================
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It is an unfortunate fact of life that hardware is often produced with
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so-called "errata", which can cause it to deviate from the architecture
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under specific circumstances. For hardware produced by ARM, these
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errata are broadly classified into the following categories:
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Category A: A critical error without a viable workaround.
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Category B: A significant or critical error with an acceptable
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workaround.
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Category C: A minor error that is not expected to occur under normal
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operation.
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For more information, consult one of the "Software Developers Errata
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Notice" documents available on infocenter.arm.com (registration
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required).
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As far as Xen is concerned, Category B errata may require some special
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treatment in the hypervisor. For example, avoiding a particular sequence
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of code, or configuring the processor in a particular way. A less common
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situation may require similar actions in order to declassify a Category A
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erratum into a Category C erratum. These are collectively known as
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"software workarounds" and are only required in the minority of cases
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(e.g. those cases that both require a non-secure workaround *and* can
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be triggered by Xen).
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For software workarounds that may adversely impact systems unaffected by
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the erratum in question, a Kconfig entry is added under "ARM errata
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workarounds via the alternatives framework". These are enabled by default
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and patched in at runtime when an affected CPU is detected. Note that
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runtime patching is only supported on ARM64. For less-intrusive workarounds,
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a Kconfig option is not available and the code is structured (preferably
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with a comment) in such a way that the erratum will not be hit.
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This approach can make it slightly onerous to determine exactly which
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errata are worked around in an arbitrary hypervisor source tree, so this
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file acts as a registry of software workarounds in the Xen hypervisor and
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will be updated when new workarounds are committed and backported to
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stable hypervisors.
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| Implementor | Component | Erratum ID | Kconfig |
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+----------------+-----------------+-----------------+-------------------------+
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| ARM | Cortex-A15 | #766422 | N/A |
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| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
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| ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
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| ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
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| ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 |
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| ARM | Cortex-A55 | #1530923 | N/A |
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| ARM | Cortex-A57 | #852523 | N/A |
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| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
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| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
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| ARM | Cortex-A57 | #1319537 | N/A |
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| ARM | Cortex-A72 | #1319367 | N/A |
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| ARM | Cortex-A72 | #853709 | N/A |
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| ARM | Cortex-A73 | #858921 | ARM_ERRATUM_858921 |
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| ARM | Cortex-A76 | #1165522 | N/A |
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| ARM | Cortex-A76 | #1286807 | ARM64_ERRATUM_1286807 |
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| ARM | Neoverse-N1 | #1165522 | N/A
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| ARM | Neoverse-N1 | #1286807 | ARM64_ERRATUM_1286807 |
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| ARM | MMU-500 | #842869 | N/A |
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