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https://github.com/xen-project/xen.git
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Ian Campbell
443701ef0c
As recommended in http://www.gnu.org/licenses/gpl-howto.en.html. This is the result of: $ git grep -El Mass\|Temple\|Franklin | xargs ./fsf.pl Where fsf.pl is: #!/usr/bin/perl -w -pi.bak -0777 my $repl = 'If not, see <http://www.gnu.org/licenses/>.'; my $br = qr/(?:\s*\n\s*(?:[\*\#]|\/\/|\.\\" )?\s*|\s+)/; my $inwt = qr/[Ii]f${br}not,${br}write${br}(?:to${br})?the${br}Free${br}Software${br}Foundation,(?:${br}Inc\.,)?/; my $mass = qr/675${br}Mass${br}Ave,?${br}Cambridge,?${br}MA${br}02139,?${br}USA,?\.?/; my $franklin = qr/51${br}Franklin${br}St(?:reet)?(?:,${br}| - )Fifth${br}Floor,?${br}Boston,?${br}MA,?${br}02110-1301,?${br}USA,?\.?/; my $temple = qr/59${br}Temple${br}Place(?:,${br}| - )Suite${br}330,?${br}Boston,?${br}MA,?${br}021110?-1307,?${br}USA,?\.?/; s|$inwt$br$mass|$repl|m; s|$inwt$br$franklin|$repl|m; s|$inwt$br$temple|$repl|m; The only remaining mentions of these addresses are in COPYING files which I haven't touched. Some of the changed files are imports from elsewhere, however filtering them out is tricky, I think it is tolerable to have these files be modified here and then perhaps reverted on the next sync, since it's only 1-2 lines and obvious what is going on. Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
542 lines
19 KiB
C
542 lines
19 KiB
C
/*
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* pci.c: HVM PCI setup.
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*
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* Leendert van Doorn, leendert@watson.ibm.com
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* Copyright (c) 2005, International Business Machines Corporation.
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*
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* Copyright (c) 2006, Keir Fraser, XenSource Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "util.h"
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#include "hypercall.h"
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#include "config.h"
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#include "pci_regs.h"
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#include <xen/memory.h>
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#include <xen/hvm/ioreq.h>
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#include <xen/hvm/hvm_xs_strings.h>
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#include <xen/hvm/e820.h>
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#include <stdbool.h>
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unsigned long pci_mem_start = HVM_BELOW_4G_MMIO_START;
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unsigned long pci_mem_end = PCI_MEM_END;
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uint64_t pci_hi_mem_start = 0, pci_hi_mem_end = 0;
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enum virtual_vga virtual_vga = VGA_none;
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unsigned long igd_opregion_pgbase = 0;
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/* Check if the specified range conflicts with any reserved device memory. */
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static bool check_overlap_all(uint64_t start, uint64_t size)
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{
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unsigned int i;
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for ( i = 0; i < memory_map.nr_map; i++ )
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{
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if ( memory_map.map[i].type == E820_RESERVED &&
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check_overlap(start, size,
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memory_map.map[i].addr,
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memory_map.map[i].size) )
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return true;
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}
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return false;
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}
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/* Find the lowest RMRR ending above base but below 4G. */
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static int find_next_rmrr(uint32_t base)
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{
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unsigned int i;
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int next_rmrr = -1;
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uint64_t end, min_end = 1ULL << 32;
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for ( i = 0; i < memory_map.nr_map ; i++ )
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{
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end = memory_map.map[i].addr + memory_map.map[i].size;
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if ( memory_map.map[i].type == E820_RESERVED &&
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end > base && end <= min_end )
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{
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next_rmrr = i;
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min_end = end;
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}
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}
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return next_rmrr;
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}
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void pci_setup(void)
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{
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uint8_t is_64bar, using_64bar, bar64_relocate = 0;
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uint32_t devfn, bar_reg, cmd, bar_data, bar_data_upper;
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uint64_t base, bar_sz, bar_sz_upper, mmio_total = 0;
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uint32_t vga_devfn = 256;
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uint16_t class, vendor_id, device_id;
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unsigned int bar, pin, link, isa_irq;
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int next_rmrr;
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/* Resources assignable to PCI devices via BARs. */
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struct resource {
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uint64_t base, max;
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} *resource, mem_resource, high_mem_resource, io_resource;
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/* Create a list of device BARs in descending order of size. */
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struct bars {
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uint32_t is_64bar;
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uint32_t devfn;
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uint32_t bar_reg;
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uint64_t bar_sz;
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} *bars = (struct bars *)scratch_start;
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unsigned int i, nr_bars = 0;
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uint64_t mmio_hole_size = 0;
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const char *s;
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/*
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* Do we allow hvmloader to relocate guest memory in order to
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* increase the size of the lowmem MMIO hole? Defaulting to 1
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* here will mean that non-libxl toolstacks (including xend and
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* home-grown ones) means that those using qemu-xen will still
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* experience the memory relocation bug described below; but it
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* also means that those using qemu-traditional will *not*
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* experience any change; and it also means that there is a
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* work-around for those using qemu-xen, namely switching to
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* qemu-traditional.
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*
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* If we defaulted to 0, and failing to resize the hole caused any
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* problems with qemu-traditional, then there is no work-around.
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*
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* Since xend can only use qemu-traditional, I think this is the
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* option that will have the least impact.
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*/
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bool allow_memory_relocate = 1;
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s = xenstore_read(HVM_XS_ALLOW_MEMORY_RELOCATE, NULL);
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if ( s )
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allow_memory_relocate = strtoll(s, NULL, 0);
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printf("Relocating guest memory for lowmem MMIO space %s\n",
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allow_memory_relocate?"enabled":"disabled");
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s = xenstore_read("platform/mmio_hole_size", NULL);
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if ( s )
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mmio_hole_size = strtoll(s, NULL, 0);
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/* Program PCI-ISA bridge with appropriate link routes. */
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isa_irq = 0;
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for ( link = 0; link < 4; link++ )
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{
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do { isa_irq = (isa_irq + 1) & 15;
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} while ( !(PCI_ISA_IRQ_MASK & (1U << isa_irq)) );
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pci_writeb(PCI_ISA_DEVFN, 0x60 + link, isa_irq);
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printf("PCI-ISA link %u routed to IRQ%u\n", link, isa_irq);
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}
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/* Program ELCR to match PCI-wired IRQs. */
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outb(0x4d0, (uint8_t)(PCI_ISA_IRQ_MASK >> 0));
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outb(0x4d1, (uint8_t)(PCI_ISA_IRQ_MASK >> 8));
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/* Scan the PCI bus and map resources. */
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for ( devfn = 0; devfn < 256; devfn++ )
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{
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class = pci_readw(devfn, PCI_CLASS_DEVICE);
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vendor_id = pci_readw(devfn, PCI_VENDOR_ID);
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device_id = pci_readw(devfn, PCI_DEVICE_ID);
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if ( (vendor_id == 0xffff) && (device_id == 0xffff) )
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continue;
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ASSERT((devfn != PCI_ISA_DEVFN) ||
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((vendor_id == 0x8086) && (device_id == 0x7000)));
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switch ( class )
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{
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case 0x0300:
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/* If emulated VGA is found, preserve it as primary VGA. */
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if ( (vendor_id == 0x1234) && (device_id == 0x1111) )
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{
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vga_devfn = devfn;
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virtual_vga = VGA_std;
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}
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else if ( (vendor_id == 0x1013) && (device_id == 0xb8) )
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{
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vga_devfn = devfn;
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virtual_vga = VGA_cirrus;
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}
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else if ( virtual_vga == VGA_none )
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{
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vga_devfn = devfn;
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virtual_vga = VGA_pt;
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if ( vendor_id == 0x8086 )
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{
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igd_opregion_pgbase = mem_hole_alloc(IGD_OPREGION_PAGES);
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/*
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* Write the the OpRegion offset to give the opregion
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* address to the device model. The device model will trap
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* and map the OpRegion at the give address.
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*/
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pci_writel(vga_devfn, PCI_INTEL_OPREGION,
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igd_opregion_pgbase << PAGE_SHIFT);
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}
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}
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break;
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case 0x0680:
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/* PIIX4 ACPI PM. Special device with special PCI config space. */
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ASSERT((vendor_id == 0x8086) && (device_id == 0x7113));
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pci_writew(devfn, 0x20, 0x0000); /* No smb bus IO enable */
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pci_writew(devfn, 0xd2, 0x0000); /* No smb bus IO enable */
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pci_writew(devfn, 0x22, 0x0000);
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pci_writew(devfn, 0x3c, 0x0009); /* Hardcoded IRQ9 */
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pci_writew(devfn, 0x3d, 0x0001);
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pci_writel(devfn, 0x40, ACPI_PM1A_EVT_BLK_ADDRESS_V1 | 1);
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pci_writeb(devfn, 0x80, 0x01); /* enable PM io space */
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break;
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case 0x0101:
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if ( vendor_id == 0x8086 )
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{
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/* Intel ICHs since PIIX3: enable IDE legacy mode. */
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pci_writew(devfn, 0x40, 0x8000); /* enable IDE0 */
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pci_writew(devfn, 0x42, 0x8000); /* enable IDE1 */
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}
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break;
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}
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/* Map the I/O memory and port resources. */
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for ( bar = 0; bar < 7; bar++ )
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{
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bar_sz_upper = 0;
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bar_reg = PCI_BASE_ADDRESS_0 + 4*bar;
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if ( bar == 6 )
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bar_reg = PCI_ROM_ADDRESS;
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bar_data = pci_readl(devfn, bar_reg);
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if ( bar_reg != PCI_ROM_ADDRESS )
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{
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is_64bar = !!((bar_data & (PCI_BASE_ADDRESS_SPACE |
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PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
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(PCI_BASE_ADDRESS_SPACE_MEMORY |
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PCI_BASE_ADDRESS_MEM_TYPE_64));
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pci_writel(devfn, bar_reg, ~0);
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}
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else
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{
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is_64bar = 0;
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pci_writel(devfn, bar_reg,
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(bar_data | PCI_ROM_ADDRESS_MASK) &
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~PCI_ROM_ADDRESS_ENABLE);
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}
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bar_sz = pci_readl(devfn, bar_reg);
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pci_writel(devfn, bar_reg, bar_data);
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if ( bar_reg != PCI_ROM_ADDRESS )
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bar_sz &= (((bar_data & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_MEMORY) ?
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PCI_BASE_ADDRESS_MEM_MASK :
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(PCI_BASE_ADDRESS_IO_MASK & 0xffff));
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else
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bar_sz &= PCI_ROM_ADDRESS_MASK;
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if (is_64bar) {
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bar_data_upper = pci_readl(devfn, bar_reg + 4);
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pci_writel(devfn, bar_reg + 4, ~0);
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bar_sz_upper = pci_readl(devfn, bar_reg + 4);
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pci_writel(devfn, bar_reg + 4, bar_data_upper);
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bar_sz = (bar_sz_upper << 32) | bar_sz;
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}
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bar_sz &= ~(bar_sz - 1);
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if ( bar_sz == 0 )
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continue;
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for ( i = 0; i < nr_bars; i++ )
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if ( bars[i].bar_sz < bar_sz )
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break;
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if ( i != nr_bars )
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memmove(&bars[i+1], &bars[i], (nr_bars-i) * sizeof(*bars));
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bars[i].is_64bar = is_64bar;
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bars[i].devfn = devfn;
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bars[i].bar_reg = bar_reg;
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bars[i].bar_sz = bar_sz;
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if ( ((bar_data & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_MEMORY) ||
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(bar_reg == PCI_ROM_ADDRESS) )
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mmio_total += bar_sz;
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nr_bars++;
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/*The upper half is already calculated, skip it! */
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if (is_64bar)
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bar++;
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}
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/* Map the interrupt. */
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pin = pci_readb(devfn, PCI_INTERRUPT_PIN);
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if ( pin != 0 )
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{
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/* This is the barber's pole mapping used by Xen. */
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link = ((pin - 1) + (devfn >> 3)) & 3;
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isa_irq = pci_readb(PCI_ISA_DEVFN, 0x60 + link);
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pci_writeb(devfn, PCI_INTERRUPT_LINE, isa_irq);
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printf("pci dev %02x:%x INT%c->IRQ%u\n",
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devfn>>3, devfn&7, 'A'+pin-1, isa_irq);
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}
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/* Enable bus mastering. */
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cmd = pci_readw(devfn, PCI_COMMAND);
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cmd |= PCI_COMMAND_MASTER;
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pci_writew(devfn, PCI_COMMAND, cmd);
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}
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if ( mmio_hole_size )
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{
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uint64_t max_ram_below_4g = (1ULL << 32) - mmio_hole_size;
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if ( max_ram_below_4g > HVM_BELOW_4G_MMIO_START )
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{
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printf("max_ram_below_4g=0x"PRIllx
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" too big for mmio_hole_size=0x"PRIllx
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" has been ignored.\n",
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PRIllx_arg(max_ram_below_4g),
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PRIllx_arg(mmio_hole_size));
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}
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else
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{
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pci_mem_start = max_ram_below_4g;
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printf("pci_mem_start=0x%lx (was 0x%x) for mmio_hole_size=%lu\n",
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pci_mem_start, HVM_BELOW_4G_MMIO_START,
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(long)mmio_hole_size);
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}
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}
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else
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{
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/*
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* At the moment qemu-xen can't deal with relocated memory regions.
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* It's too close to the release to make a proper fix; for now,
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* only allow the MMIO hole to grow large enough to move guest memory
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* if we're running qemu-traditional. Items that don't fit will be
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* relocated into the 64-bit address space.
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*
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* This loop now does the following:
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* - If allow_memory_relocate, increase the MMIO hole until it's
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* big enough, or until it's 2GiB
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* - If !allow_memory_relocate, increase the MMIO hole until it's
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* big enough, or until it's 2GiB, or until it overlaps guest
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* memory
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*/
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while ( (mmio_total > (pci_mem_end - pci_mem_start))
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&& ((pci_mem_start << 1) != 0)
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&& (allow_memory_relocate
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|| (((pci_mem_start << 1) >> PAGE_SHIFT)
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>= hvm_info->low_mem_pgend)) )
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pci_mem_start <<= 1;
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/*
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* Try to accommodate RMRRs in our MMIO region on a best-effort basis.
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* If we have RMRRs in the range, then make pci_mem_start just after
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* hvm_info->low_mem_pgend.
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*/
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if ( pci_mem_start > (hvm_info->low_mem_pgend << PAGE_SHIFT) &&
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check_overlap_all(pci_mem_start, pci_mem_end-pci_mem_start) )
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pci_mem_start = hvm_info->low_mem_pgend << PAGE_SHIFT;
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}
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if ( mmio_total > (pci_mem_end - pci_mem_start) )
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{
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printf("Low MMIO hole not large enough for all devices,"
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" relocating some BARs to 64-bit\n");
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bar64_relocate = 1;
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}
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/* Relocate RAM that overlaps PCI space (in 64k-page chunks). */
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while ( (pci_mem_start >> PAGE_SHIFT) < hvm_info->low_mem_pgend )
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{
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struct xen_add_to_physmap xatp;
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unsigned int nr_pages = min_t(
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unsigned int,
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hvm_info->low_mem_pgend - (pci_mem_start >> PAGE_SHIFT),
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(1u << 16) - 1);
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if ( hvm_info->high_mem_pgend == 0 )
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hvm_info->high_mem_pgend = 1ull << (32 - PAGE_SHIFT);
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hvm_info->low_mem_pgend -= nr_pages;
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printf("Relocating 0x%x pages from "PRIllx" to "PRIllx\
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" for lowmem MMIO hole\n",
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nr_pages,
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PRIllx_arg(((uint64_t)hvm_info->low_mem_pgend)<<PAGE_SHIFT),
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PRIllx_arg(((uint64_t)hvm_info->high_mem_pgend)<<PAGE_SHIFT));
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xatp.domid = DOMID_SELF;
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xatp.space = XENMAPSPACE_gmfn_range;
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xatp.idx = hvm_info->low_mem_pgend;
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xatp.gpfn = hvm_info->high_mem_pgend;
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xatp.size = nr_pages;
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if ( hypercall_memory_op(XENMEM_add_to_physmap, &xatp) != 0 )
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BUG();
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hvm_info->high_mem_pgend += nr_pages;
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}
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/* Sync memory map[] if necessary. */
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adjust_memory_map();
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high_mem_resource.base = ((uint64_t)hvm_info->high_mem_pgend) << PAGE_SHIFT;
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if ( high_mem_resource.base < 1ull << 32 )
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{
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if ( hvm_info->high_mem_pgend != 0 )
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printf("WARNING: hvm_info->high_mem_pgend %x"
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" does not point into high memory!",
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hvm_info->high_mem_pgend);
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high_mem_resource.base = 1ull << 32;
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}
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printf("%sRAM in high memory; setting high_mem resource base to "PRIllx"\n",
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hvm_info->high_mem_pgend?"":"No ",
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PRIllx_arg(high_mem_resource.base));
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high_mem_resource.max = 1ull << cpu_phys_addr();
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mem_resource.base = pci_mem_start;
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mem_resource.max = pci_mem_end;
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io_resource.base = 0xc000;
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io_resource.max = 0x10000;
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next_rmrr = find_next_rmrr(pci_mem_start);
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/* Assign iomem and ioport resources in descending order of size. */
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for ( i = 0; i < nr_bars; i++ )
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{
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devfn = bars[i].devfn;
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bar_reg = bars[i].bar_reg;
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bar_sz = bars[i].bar_sz;
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/*
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* Relocate to high memory if the total amount of MMIO needed
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* is more than the low MMIO available. Because devices are
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* processed in order of bar_sz, this will preferentially
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* relocate larger devices to high memory first.
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*
|
|
* NB: The code here is rather fragile, as the check here to see
|
|
* whether bar_sz will fit in the low MMIO region doesn't match the
|
|
* real check made below, which involves aligning the base offset of the
|
|
* bar with the size of the bar itself. As it happens, this will always
|
|
* be satisfied because:
|
|
* - The first one will succeed because the MMIO hole can only start at
|
|
* 0x{f,e,c,8}00000000. If it fits, it will be aligned properly.
|
|
* - All subsequent ones will be aligned because the list is ordered
|
|
* large to small, and bar_sz is always a power of 2. (At least
|
|
* the code here assumes it to be.)
|
|
* Should either of those two conditions change, this code will break.
|
|
*/
|
|
using_64bar = bars[i].is_64bar && bar64_relocate
|
|
&& (mmio_total > (mem_resource.max - mem_resource.base));
|
|
bar_data = pci_readl(devfn, bar_reg);
|
|
|
|
if ( (bar_data & PCI_BASE_ADDRESS_SPACE) ==
|
|
PCI_BASE_ADDRESS_SPACE_MEMORY )
|
|
{
|
|
/* Mapping high memory if PCI device is 64 bits bar */
|
|
if ( using_64bar ) {
|
|
if ( high_mem_resource.base & (bar_sz - 1) )
|
|
high_mem_resource.base = high_mem_resource.base -
|
|
(high_mem_resource.base & (bar_sz - 1)) + bar_sz;
|
|
if ( !pci_hi_mem_start )
|
|
pci_hi_mem_start = high_mem_resource.base;
|
|
resource = &high_mem_resource;
|
|
bar_data &= ~PCI_BASE_ADDRESS_MEM_MASK;
|
|
}
|
|
else {
|
|
resource = &mem_resource;
|
|
bar_data &= ~PCI_BASE_ADDRESS_MEM_MASK;
|
|
}
|
|
mmio_total -= bar_sz;
|
|
}
|
|
else
|
|
{
|
|
resource = &io_resource;
|
|
bar_data &= ~PCI_BASE_ADDRESS_IO_MASK;
|
|
}
|
|
|
|
base = (resource->base + bar_sz - 1) & ~(uint64_t)(bar_sz - 1);
|
|
|
|
/* If we're using mem_resource, check for RMRR conflicts. */
|
|
while ( resource == &mem_resource &&
|
|
next_rmrr >= 0 &&
|
|
check_overlap(base, bar_sz,
|
|
memory_map.map[next_rmrr].addr,
|
|
memory_map.map[next_rmrr].size) )
|
|
{
|
|
base = memory_map.map[next_rmrr].addr + memory_map.map[next_rmrr].size;
|
|
base = (base + bar_sz - 1) & ~(bar_sz - 1);
|
|
next_rmrr = find_next_rmrr(base);
|
|
}
|
|
|
|
bar_data |= (uint32_t)base;
|
|
bar_data_upper = (uint32_t)(base >> 32);
|
|
base += bar_sz;
|
|
|
|
if ( (base < resource->base) || (base > resource->max) )
|
|
{
|
|
printf("pci dev %02x:%x bar %02x size "PRIllx": no space for "
|
|
"resource!\n", devfn>>3, devfn&7, bar_reg,
|
|
PRIllx_arg(bar_sz));
|
|
continue;
|
|
}
|
|
|
|
resource->base = base;
|
|
|
|
pci_writel(devfn, bar_reg, bar_data);
|
|
if (using_64bar)
|
|
pci_writel(devfn, bar_reg + 4, bar_data_upper);
|
|
printf("pci dev %02x:%x bar %02x size "PRIllx": %x%08x\n",
|
|
devfn>>3, devfn&7, bar_reg,
|
|
PRIllx_arg(bar_sz),
|
|
bar_data_upper, bar_data);
|
|
|
|
|
|
/* Now enable the memory or I/O mapping. */
|
|
cmd = pci_readw(devfn, PCI_COMMAND);
|
|
if ( (bar_reg == PCI_ROM_ADDRESS) ||
|
|
((bar_data & PCI_BASE_ADDRESS_SPACE) ==
|
|
PCI_BASE_ADDRESS_SPACE_MEMORY) )
|
|
cmd |= PCI_COMMAND_MEMORY;
|
|
else
|
|
cmd |= PCI_COMMAND_IO;
|
|
pci_writew(devfn, PCI_COMMAND, cmd);
|
|
}
|
|
|
|
if ( pci_hi_mem_start )
|
|
{
|
|
/*
|
|
* Make end address alignment match the start address one's so that
|
|
* fewer variable range MTRRs are needed to cover the range.
|
|
*/
|
|
pci_hi_mem_end = ((high_mem_resource.base - 1) |
|
|
((pci_hi_mem_start & -pci_hi_mem_start) - 1)) + 1;
|
|
}
|
|
|
|
if ( vga_devfn != 256 )
|
|
{
|
|
/*
|
|
* VGA registers live in I/O space so ensure that primary VGA
|
|
* has IO enabled, even if there is no I/O BAR on that
|
|
* particular device.
|
|
*/
|
|
cmd = pci_readw(vga_devfn, PCI_COMMAND);
|
|
cmd |= PCI_COMMAND_IO;
|
|
pci_writew(vga_devfn, PCI_COMMAND, cmd);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Local variables:
|
|
* mode: C
|
|
* c-file-style: "BSD"
|
|
* c-basic-offset: 4
|
|
* tab-width: 4
|
|
* indent-tabs-mode: nil
|
|
* End:
|
|
*/
|