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Contemporary processors are gaining Indirect Branch Controls via microcode updates. Intel are introducing one bit to indicate IBRS and IBPB support, and a second bit for STIBP. AMD are introducing IBPB only, so enumerate it with a separate bit. Furthermore, depending on compiler and microcode availability, we may want to run Xen with IBRS set, or clear. To use these facilities, we synthesise separate IBRS and IBPB bits for internal use. A lot of infrastructure is required before these features are safe to offer to guests. This is part of XSA-254. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> Acked-by: Wei Liu <wei.liu2@citrix.com>