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rneugeba@wyvis.research.intel-research.net
ab5301ae22
various hacks for batching mode and stats gathering Signed-off-by: michael.fetterman@cl.cam.ac.uk
302 lines
7.6 KiB
C
302 lines
7.6 KiB
C
/*
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* User mode program to program performance counters.
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*
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* JRB/IAP October 2003.
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*
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* $Id: cpuperf.c,v 1.2 2003/10/14 11:00:59 jrb44 Exp $
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*
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* $Log: cpuperf.c,v $
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* Revision 1.2 2003/10/14 11:00:59 jrb44
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* Added dcefault CPU. Added NONE CCCR.
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*
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* Revision 1.1 2003/10/13 16:49:44 jrb44
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* Initial revision
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*
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*/
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#include <sys/types.h>
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#include <sched.h>
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#include <error.h>
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#include <stdio.h>
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#include <unistd.h>
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#include <stdlib.h>
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#include <string.h>
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#include <errno.h>
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#include "p4perf.h"
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static inline void cpus_wrmsr(int cpu_mask,
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int msr,
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unsigned int low,
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unsigned int high )
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{
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fprintf(stderr, "No backend to write MSR 0x%x <= 0x%08x%08x on %08x\n",
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msr, high, low, cpu_mask);
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}
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static inline unsigned long long cpus_rdmsr( int cpu_mask, int msr )
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{
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fprintf(stderr, "No backend to read MSR 0x%x on %08x\n", msr, cpu_mask);
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return 0;
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}
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#ifdef PERFCNTR
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#include "cpuperf_perfcntr.h"
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#define cpus_wrmsr perfcntr_wrmsr
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#define cpus_rdmsr perfcntr_rdmsr
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#endif
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#ifdef XENO
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#include "cpuperf_xeno.h"
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#define cpus_wrmsr dom0_wrmsr
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#define cpus_rdmsr dom0_rdmsr
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#endif
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struct macros {
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char *name;
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unsigned long msr_addr;
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int number;
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};
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#define NO_CCCR 0xfffffffe
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struct macros msr[] = {
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{"BPU_COUNTER0", 0x300, 0},
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{"BPU_COUNTER1", 0x301, 1},
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{"BPU_COUNTER2", 0x302, 2},
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{"BPU_COUNTER3", 0x303, 3},
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{"MS_COUNTER0", 0x304, 4},
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{"MS_COUNTER1", 0x305, 5},
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{"MS_COUNTER2", 0x306, 6},
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{"MS_COUNTER3", 0x307, 7},
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{"FLAME_COUNTER0", 0x308, 8},
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{"FLAME_COUNTER1", 0x309, 9},
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{"FLAME_COUNTER2", 0x30a, 10},
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{"FLAME_COUNTER3", 0x30b, 11},
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{"IQ_COUNTER0", 0x30c, 12},
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{"IQ_COUNTER1", 0x30d, 13},
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{"IQ_COUNTER2", 0x30e, 14},
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{"IQ_COUNTER3", 0x30f, 15},
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{"IQ_COUNTER4", 0x310, 16},
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{"IQ_COUNTER5", 0x311, 17},
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{"BPU_CCCR0", 0x360, 0},
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{"BPU_CCCR1", 0x361, 1},
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{"BPU_CCCR2", 0x362, 2},
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{"BPU_CCCR3", 0x363, 3},
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{"MS_CCCR0", 0x364, 4},
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{"MS_CCCR1", 0x365, 5},
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{"MS_CCCR2", 0x366, 6},
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{"MS_CCCR3", 0x367, 7},
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{"FLAME_CCCR0", 0x368, 8},
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{"FLAME_CCCR1", 0x369, 9},
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{"FLAME_CCCR2", 0x36a, 10},
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{"FLAME_CCCR3", 0x36b, 11},
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{"IQ_CCCR0", 0x36c, 12},
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{"IQ_CCCR1", 0x36d, 13},
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{"IQ_CCCR2", 0x36e, 14},
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{"IQ_CCCR3", 0x36f, 15},
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{"IQ_CCCR4", 0x370, 16},
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{"IQ_CCCR5", 0x371, 17},
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{"BSU_ESCR0", 0x3a0, 7},
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{"BSU_ESCR1", 0x3a1, 7},
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{"FSB_ESCR0", 0x3a2, 6},
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{"FSB_ESCR1", 0x3a3, 6},
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{"MOB_ESCR0", 0x3aa, 2},
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{"MOB_ESCR1", 0x3ab, 2},
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{"PMH_ESCR0", 0x3ac, 4},
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{"PMH_ESCR1", 0x3ad, 4},
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{"BPU_ESCR0", 0x3b2, 0},
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{"BPU_ESCR1", 0x3b3, 0},
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{"IS_ESCR0", 0x3b4, 1},
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{"IS_ESCR1", 0x3b5, 1},
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{"ITLB_ESCR0", 0x3b6, 3},
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{"ITLB_ESCR1", 0x3b7, 3},
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{"IX_ESCR0", 0x3c8, 5},
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{"IX_ESCR1", 0x3c9, 5},
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{"MS_ESCR0", 0x3c0, 0},
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{"MS_ESCR1", 0x3c1, 0},
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{"TBPU_ESCR0", 0x3c2, 2},
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{"TBPU_ESCR1", 0x3c3, 2},
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{"TC_ESCR0", 0x3c4, 1},
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{"TC_ESCR1", 0x3c5, 1},
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{"FIRM_ESCR0", 0x3a4, 1},
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{"FIRM_ESCR1", 0x3a5, 1},
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{"FLAME_ESCR0", 0x3a6, 0},
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{"FLAME_ESCR1", 0x3a7, 0},
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{"DAC_ESCR0", 0x3a8, 5},
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{"DAC_ESCR1", 0x3a9, 5},
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{"SAAT_ESCR0", 0x3ae, 2},
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{"SAAT_ESCR1", 0x3af, 2},
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{"U2L_ESCR0", 0x3b0, 3},
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{"U2L_ESCR1", 0x3b1, 3},
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{"CRU_ESCR0", 0x3b8, 4},
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{"CRU_ESCR1", 0x3b9, 4},
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{"CRU_ESCR2", 0x3cc, 5},
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{"CRU_ESCR3", 0x3cd, 5},
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{"CRU_ESCR4", 0x3e0, 6},
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{"CRU_ESCR5", 0x3e1, 6},
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{"IQ_ESCR0", 0x3ba, 0},
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{"IQ_ESCR1", 0x3bb, 0},
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{"RAT_ESCR0", 0x3bc, 2},
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{"RAT_ESCR1", 0x3bd, 2},
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{"SSU_ESCR0", 0x3be, 3},
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{"SSU_ESCR1", 0x3bf, 3},
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{"ALF_ESCR0", 0x3ca, 1},
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{"ALF_ESCR1", 0x3cb, 1},
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{"PEBS_ENABLE", 0x3f1, 0},
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{"PEBS_MATRIX_VERT", 0x3f2, 0},
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{"NONE", NO_CCCR, 0},
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{NULL, 0, 0}
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};
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struct macros *lookup_macro(char *str)
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{
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struct macros *m;
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m = msr;
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while (m->name) {
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if (strcmp(m->name, str) == 0)
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return m;
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m++;
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}
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return NULL;
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}
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int main(int argc, char **argv)
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{
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int c, t = 0xc, es = 0, em = 0, tv = 0, te = 0;
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unsigned int cpu_mask = 1;
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struct macros *escr = NULL, *cccr = NULL;
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unsigned long escr_val, cccr_val;
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int debug = 0;
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unsigned long pebs = 0, pebs_vert = 0;
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int pebs_x = 0, pebs_vert_x = 0;
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int read = 0;
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int compare = 0;
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int complement = 0;
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int edge = 0;
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#ifdef XENO
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xen_init();
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#endif
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while ((c = getopt(argc, argv, "dc:t:e:m:T:E:C:P:V:rkng")) != -1) {
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switch((char)c) {
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case 'P':
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pebs |= 1 << atoi(optarg);
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pebs_x = 1;
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break;
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case 'V':
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pebs_vert |= 1 << atoi(optarg);
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pebs_vert_x = 1;
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break;
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case 'd':
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debug = 1;
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break;
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case 'c':
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{
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int cpu = atoi(optarg);
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cpu_mask = (cpu == -1)?(~0):(1<<cpu);
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}
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break;
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case 't': // ESCR thread bits
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t = atoi(optarg);
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break;
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case 'e': // eventsel
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es = atoi(optarg);
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break;
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case 'm': // eventmask
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em = atoi(optarg);
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break;
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case 'T': // tag value
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tv = atoi(optarg);
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te = 1;
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break;
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case 'E':
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escr = lookup_macro(optarg);
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if (!escr) {
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fprintf(stderr, "Macro '%s' not found.\n", optarg);
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exit(1);
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}
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break;
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case 'C':
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cccr = lookup_macro(optarg);
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if (!cccr) {
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fprintf(stderr, "Macro '%s' not found.\n", optarg);
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exit(1);
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}
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break;
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case 'r':
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read = 1;
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break;
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case 'k':
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compare = 1;
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break;
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case 'n':
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complement = 1;
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break;
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case 'g':
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edge = 1;
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break;
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}
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}
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if (read) {
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while((cpu_mask&1)) {
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int i;
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for (i=0x300;i<0x312;i++) {
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printf("%010llu ",cpus_rdmsr( cpu_mask, i ) );
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}
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printf("\n");
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cpu_mask>>=1;
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}
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exit(1);
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}
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if (!escr) {
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fprintf(stderr, "Need an ESCR.\n");
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exit(1);
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}
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if (!cccr) {
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fprintf(stderr, "Need a counter number.\n");
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exit(1);
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}
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escr_val = P4_ESCR_THREADS(t) | P4_ESCR_EVNTSEL(es) |
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P4_ESCR_EVNTMASK(em) | P4_ESCR_TV(tv) | ((te)?P4_ESCR_TE:0);
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cccr_val = P4_CCCR_ENABLE | P4_CCCR_ESCR(escr->number) |
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((compare)?P4_CCCR_COMPARE:0) |
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((complement)?P4_CCCR_COMPLEMENT:0) |
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((edge)?P4_CCCR_EDGE:0) |
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P4_CCCR_ACTIVE_THREAD(3)/*reserved*/;
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if (debug) {
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fprintf(stderr, "ESCR 0x%lx <= 0x%08lx\n", escr->msr_addr, escr_val);
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if (cccr->msr_addr != NO_CCCR)
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fprintf(stderr, "CCCR 0x%lx <= 0x%08lx (%u)\n",
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cccr->msr_addr, cccr_val, cccr->number);
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if (pebs_x)
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fprintf(stderr, "PEBS 0x%x <= 0x%08lx\n",
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MSR_P4_PEBS_ENABLE, pebs);
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if (pebs_vert_x)
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fprintf(stderr, "PMV 0x%x <= 0x%08lx\n",
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MSR_P4_PEBS_MATRIX_VERT, pebs_vert);
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}
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cpus_wrmsr( cpu_mask, escr->msr_addr, escr_val, 0 );
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if (cccr->msr_addr != NO_CCCR)
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cpus_wrmsr( cpu_mask, cccr->msr_addr, cccr_val, 0 );
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if (pebs_x)
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cpus_wrmsr( cpu_mask, MSR_P4_PEBS_ENABLE, pebs, 0 );
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if (pebs_vert_x)
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cpus_wrmsr( cpu_mask, MSR_P4_PEBS_MATRIX_VERT, pebs_vert, 0 );
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return 0;
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}
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// End of $RCSfile: cpuperf.c,v $
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