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Manish Jaggi
66158be465
This patch extends the gicv3_iomem_deny_access functionality by adding support for ITS region as well. Add function gicv3_its_deny_access. Signed-off-by: Manish Jaggi <mjaggi@cavium.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Julien Grall <julien.grall@arm.com>
288 lines
9.4 KiB
C
288 lines
9.4 KiB
C
/*
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* ARM GICv3 ITS support
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*
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* Andre Przywara <andre.przywara@arm.com>
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* Copyright (c) 2016,2017 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; under version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ARM_ITS_H__
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#define __ASM_ARM_ITS_H__
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#define GITS_CTLR 0x000
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#define GITS_IIDR 0x004
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#define GITS_TYPER 0x008
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#define GITS_CBASER 0x080
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#define GITS_CWRITER 0x088
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#define GITS_CREADR 0x090
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#define GITS_BASER_NR_REGS 8
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#define GITS_BASER0 0x100
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#define GITS_BASER1 0x108
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#define GITS_BASER2 0x110
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#define GITS_BASER3 0x118
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#define GITS_BASER4 0x120
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#define GITS_BASER5 0x128
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#define GITS_BASER6 0x130
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#define GITS_BASER7 0x138
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#define GITS_PIDR2 GICR_PIDR2
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/* Register bits */
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#define GITS_VALID_BIT BIT(63)
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#define GITS_CTLR_QUIESCENT BIT(31)
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#define GITS_CTLR_ENABLE BIT(0)
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#define GITS_TYPER_PTA BIT(19)
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#define GITS_TYPER_DEVIDS_SHIFT 13
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#define GITS_TYPER_DEVIDS_MASK (0x1fUL << GITS_TYPER_DEVIDS_SHIFT)
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#define GITS_TYPER_DEVICE_ID_BITS(r) (((r & GITS_TYPER_DEVIDS_MASK) >> \
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GITS_TYPER_DEVIDS_SHIFT) + 1)
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#define GITS_TYPER_IDBITS_SHIFT 8
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#define GITS_TYPER_IDBITS_MASK (0x1fUL << GITS_TYPER_IDBITS_SHIFT)
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#define GITS_TYPER_EVENT_ID_BITS(r) (((r & GITS_TYPER_IDBITS_MASK) >> \
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GITS_TYPER_IDBITS_SHIFT) + 1)
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#define GITS_TYPER_ITT_SIZE_SHIFT 4
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#define GITS_TYPER_ITT_SIZE_MASK (0xfUL << GITS_TYPER_ITT_SIZE_SHIFT)
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#define GITS_TYPER_ITT_SIZE(r) ((((r) & GITS_TYPER_ITT_SIZE_MASK) >> \
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GITS_TYPER_ITT_SIZE_SHIFT) + 1)
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#define GITS_TYPER_PHYSICAL (1U << 0)
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#define GITS_BASER_INDIRECT BIT(62)
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#define GITS_BASER_INNER_CACHEABILITY_SHIFT 59
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#define GITS_BASER_TYPE_SHIFT 56
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#define GITS_BASER_TYPE_MASK (7ULL << GITS_BASER_TYPE_SHIFT)
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#define GITS_BASER_OUTER_CACHEABILITY_SHIFT 53
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#define GITS_BASER_TYPE_NONE 0UL
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#define GITS_BASER_TYPE_DEVICE 1UL
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#define GITS_BASER_TYPE_VCPU 2UL
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#define GITS_BASER_TYPE_CPU 3UL
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#define GITS_BASER_TYPE_COLLECTION 4UL
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#define GITS_BASER_TYPE_RESERVED5 5UL
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#define GITS_BASER_TYPE_RESERVED6 6UL
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#define GITS_BASER_TYPE_RESERVED7 7UL
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#define GITS_BASER_ENTRY_SIZE_SHIFT 48
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#define GITS_BASER_ENTRY_SIZE(reg) \
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(((reg >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
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#define GITS_BASER_SHAREABILITY_SHIFT 10
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#define GITS_BASER_PAGE_SIZE_SHIFT 8
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#define GITS_BASER_SIZE_MASK 0xff
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#define GITS_BASER_SHAREABILITY_MASK (0x3ULL << GITS_BASER_SHAREABILITY_SHIFT)
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#define GITS_BASER_OUTER_CACHEABILITY_MASK (0x7ULL << GITS_BASER_OUTER_CACHEABILITY_SHIFT)
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#define GITS_BASER_INNER_CACHEABILITY_MASK (0x7ULL << GITS_BASER_INNER_CACHEABILITY_SHIFT)
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#define GITS_CBASER_SIZE_MASK 0xff
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/* ITS command definitions */
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#define ITS_CMD_SIZE 32
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#define GITS_CMD_MOVI 0x01
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#define GITS_CMD_INT 0x03
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#define GITS_CMD_CLEAR 0x04
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#define GITS_CMD_SYNC 0x05
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#define GITS_CMD_MAPD 0x08
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#define GITS_CMD_MAPC 0x09
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#define GITS_CMD_MAPTI 0x0a
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#define GITS_CMD_MAPI 0x0b
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#define GITS_CMD_INV 0x0c
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#define GITS_CMD_INVALL 0x0d
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#define GITS_CMD_MOVALL 0x0e
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#define GITS_CMD_DISCARD 0x0f
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#define ITS_DOORBELL_OFFSET 0x10040
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#define GICV3_ITS_SIZE SZ_128K
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#include <xen/device_tree.h>
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#include <xen/rbtree.h>
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#define HOST_ITS_FLUSH_CMD_QUEUE (1U << 0)
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#define HOST_ITS_USES_PTA (1U << 1)
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/* We allocate LPIs on the hosts in chunks of 32 to reduce handling overhead. */
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#define LPI_BLOCK 32U
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/* data structure for each hardware ITS */
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struct host_its {
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struct list_head entry;
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const struct dt_device_node *dt_node;
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paddr_t addr;
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paddr_t size;
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void __iomem *its_base;
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unsigned int devid_bits;
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unsigned int evid_bits;
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unsigned int itte_size;
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spinlock_t cmd_lock;
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void *cmd_buf;
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unsigned int flags;
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};
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#ifdef CONFIG_HAS_ITS
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extern struct list_head host_its_list;
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/* Parse the host DT and pick up all host ITSes. */
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void gicv3_its_dt_init(const struct dt_device_node *node);
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#ifdef CONFIG_ACPI
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void gicv3_its_acpi_init(void);
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#endif
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/* Deny iomem access for its */
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int gicv3_its_deny_access(const struct domain *d);
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bool gicv3_its_host_has_its(void);
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unsigned int vgic_v3_its_count(const struct domain *d);
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void gicv3_do_LPI(unsigned int lpi);
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int gicv3_lpi_init_rdist(void __iomem * rdist_base);
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/* Initialize the host structures for LPIs and the host ITSes. */
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int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits);
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int gicv3_its_init(void);
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/* Store the physical address and ID for each redistributor as read from DT. */
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void gicv3_set_redist_address(paddr_t address, unsigned int redist_id);
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uint64_t gicv3_get_redist_address(unsigned int cpu, bool use_pta);
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/* Map a collection for this host CPU to each host ITS. */
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int gicv3_its_setup_collection(unsigned int cpu);
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/* Initialize and destroy the per-domain parts of the virtual ITS support. */
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int vgic_v3_its_init_domain(struct domain *d);
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void vgic_v3_its_free_domain(struct domain *d);
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/* Create the appropriate DT nodes for a hardware domain. */
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int gicv3_its_make_hwdom_dt_nodes(const struct domain *d,
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const struct dt_device_node *gic,
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void *fdt);
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/*
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* Map a device on the host by allocating an ITT on the host (ITS).
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* "nr_event" specifies how many events (interrupts) this device will need.
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* Setting "valid" to false deallocates the device.
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*/
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int gicv3_its_map_guest_device(struct domain *d,
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paddr_t host_doorbell, uint32_t host_devid,
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paddr_t guest_doorbell, uint32_t guest_devid,
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uint64_t nr_events, bool valid);
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int gicv3_allocate_host_lpi_block(struct domain *d, uint32_t *first_lpi);
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void gicv3_free_host_lpi_block(uint32_t first_lpi);
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void vgic_vcpu_inject_lpi(struct domain *d, unsigned int virq);
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struct pending_irq *gicv3_its_get_event_pending_irq(struct domain *d,
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paddr_t vdoorbell_address,
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uint32_t vdevid,
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uint32_t eventid);
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int gicv3_remove_guest_event(struct domain *d, paddr_t vdoorbell_address,
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uint32_t vdevid, uint32_t eventid);
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struct pending_irq *gicv3_assign_guest_event(struct domain *d, paddr_t doorbell,
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uint32_t devid, uint32_t eventid,
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uint32_t virt_lpi);
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void gicv3_lpi_update_host_entry(uint32_t host_lpi, int domain_id,
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uint32_t virt_lpi);
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#else
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static inline void gicv3_its_dt_init(const struct dt_device_node *node)
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{
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}
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#ifdef CONFIG_ACPI
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static inline void gicv3_its_acpi_init(void)
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{
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}
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#endif
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static inline int gicv3_its_deny_access(const struct domain *d)
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{
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return 0;
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}
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static inline bool gicv3_its_host_has_its(void)
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{
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return false;
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}
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static inline unsigned int vgic_v3_its_count(const struct domain *d)
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{
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return 0;
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}
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static inline void gicv3_do_LPI(unsigned int lpi)
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{
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/* We don't enable LPIs without an ITS. */
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BUG();
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}
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static inline int gicv3_lpi_init_rdist(void __iomem * rdist_base)
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{
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return -ENODEV;
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}
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static inline int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits)
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{
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return 0;
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}
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static inline int gicv3_its_init(void)
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{
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return 0;
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}
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static inline void gicv3_set_redist_address(paddr_t address,
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unsigned int redist_id)
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{
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}
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static inline int gicv3_its_setup_collection(unsigned int cpu)
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{
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/* We should never get here without an ITS. */
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BUG();
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}
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static inline int vgic_v3_its_init_domain(struct domain *d)
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{
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return 0;
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}
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static inline void vgic_v3_its_free_domain(struct domain *d)
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{
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}
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static inline int gicv3_its_make_hwdom_dt_nodes(const struct domain *d,
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const struct dt_device_node *gic,
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void *fdt)
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{
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return 0;
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}
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#endif /* CONFIG_HAS_ITS */
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#endif
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/*
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* Local variables:
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* mode: C
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* c-file-style: "BSD"
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* c-basic-offset: 4
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* indent-tabs-mode: nil
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* End:
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*/
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