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kaf24@firebug.cl.cam.ac.uk
f08246e197
a) 64-bit switch_to scheduler macro (by Aravindh Puthiyaparambil) b) implements 64-bit hypervisor_callback c) fixes thread creation issues (thread_starter used to perform initialisation) Signed-off-by: Grzegorz Milos <gm281@cam.ac.uk>
96 lines
3.1 KiB
C
96 lines
3.1 KiB
C
/******************************************************************************
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* hypervisor.c
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*
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* Communication to/from hypervisor.
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*
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* Copyright (c) 2002-2003, K A Fraser
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* Copyright (c) 2005, Grzegorz Milos, gm281@cam.ac.uk,Intel Research Cambridge
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <os.h>
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#include <hypervisor.h>
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#include <events.h>
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#define active_evtchns(cpu,sh,idx) \
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((sh)->evtchn_pending[idx] & \
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~(sh)->evtchn_mask[idx])
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void do_hypervisor_callback(struct pt_regs *regs)
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{
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u32 l1, l2;
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unsigned int l1i, l2i, port;
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int cpu = 0;
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shared_info_t *s = HYPERVISOR_shared_info;
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vcpu_info_t *vcpu_info = &s->vcpu_info[cpu];
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vcpu_info->evtchn_upcall_pending = 0;
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/* NB. No need for a barrier here -- XCHG is a barrier on x86. */
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l1 = xchg(&vcpu_info->evtchn_pending_sel, 0);
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while ( l1 != 0 )
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{
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l1i = __ffs(l1);
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l1 &= ~(1 << l1i);
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while ( (l2 = active_evtchns(cpu, s, l1i)) != 0 )
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{
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l2i = __ffs(l2);
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l2 &= ~(1 << l2i);
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port = (l1i << 5) + l2i;
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do_event(port, regs);
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}
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}
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}
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inline void mask_evtchn(u32 port)
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{
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shared_info_t *s = HYPERVISOR_shared_info;
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synch_set_bit(port, &s->evtchn_mask[0]);
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}
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inline void unmask_evtchn(u32 port)
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{
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shared_info_t *s = HYPERVISOR_shared_info;
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vcpu_info_t *vcpu_info = &s->vcpu_info[smp_processor_id()];
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synch_clear_bit(port, &s->evtchn_mask[0]);
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/*
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* The following is basically the equivalent of 'hw_resend_irq'. Just like
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* a real IO-APIC we 'lose the interrupt edge' if the channel is masked.
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*/
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if ( synch_test_bit (port, &s->evtchn_pending[0]) &&
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!synch_test_and_set_bit(port>>5, &vcpu_info->evtchn_pending_sel) )
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{
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vcpu_info->evtchn_upcall_pending = 1;
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if ( !vcpu_info->evtchn_upcall_mask )
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force_evtchn_callback();
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}
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}
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inline void clear_evtchn(u32 port)
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{
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shared_info_t *s = HYPERVISOR_shared_info;
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synch_clear_bit(port, &s->evtchn_pending[0]);
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}
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