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xen/docs/misc/riscv/booting.txt
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Baptiste Le Duc 861e44a3ba xen/riscv: make Zihintpause no longer a required extension
Zihintpause is in required_extensions[] so Xen panics when it is missing,
while it does not strictly require hardware support for it.

The PAUSE hint (Zihintpause extension) is encoded as FENCE W, 0
(0x0100000F). In accordance with the RISC-V Unprivileged ISA, HINTs are
encoded in the space of valid standard instructions. On platforms without
Zihintpause support, executing 0x0100000F is treated as a standard FENCE
with an empty successor set, which acts as a NOP and never generates an
illegal instruction trap.

Zihintpause is therefore purely an optimization hint. Drop it from
required_extensions[] so Xen can still boot on systems that don't advertise
it, and print a warning in that case.

Assisted-by: Claude:claude-opus-5
Signed-off-by: Baptiste Le Duc <baptiste.le-duc@vates.tech>
Reviewed-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
2026-09-30 15:00:48 +02:00

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System requirements
===================
The following extensions are required by Xen. Xen panics at boot if any of
them is missing from the riscv,isa property of the CPU nodes:
- I, M, A, Zicsr, Zifencei:
Base ISA Xen is compiled for.
- C:
Required only when Xen is built with CONFIG_RISCV_ISA_C=y.
- H:
Provides additional instructions and CSRs that control the new stage of
address translation and support hosting a guest OS in virtual S-mode
(VS-mode).
- Zbb:
RISC-V doesn't have a CLZ instruction in the base ISA.
As a consequence, __builtin_ffs() emits a library call to ffs() on GCC,
or a de Bruijn sequence on Clang.
Zbb extension adds a CLZ instruction, after which __builtin_ffs() emits
a very simple sequence.
The similar issue occurs with other __builtin_<bitop>, so it is needed to
provide a generic version of bitops in RISC-V bitops.h
- Svpbmt:
Mandatory to enable changing the memory attributes of a page.
For platforms that do not support Svpbmt, it is necessary to introduce a
similar mechanism as described in:
https://lore.kernel.org/all/20241102000843.1301099-1-samuel.holland@sifive.com/
Note: this list must be kept in sync with required_extensions[] in
xen/arch/riscv/cpufeature.c.
Optional extensions
===================
Other extensions recognised by Xen are listed in riscv_isa_ext[] in
xen/arch/riscv/cpufeature.c. Xen uses them when present, but they are not
needed to boot. The second column of that table says whether the extension
is also exposed to guests.