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112 lines
3.9 KiB
C
112 lines
3.9 KiB
C
/* -*- Mode:C; c-basic-offset:4; tab-width:4 -*-
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*
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* (C) 2003 - Rolf Neugebauer - Intel Research Cambridge
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* Copyright (c) 2005, Keir A Fraser
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _MM_H_
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#define _MM_H_
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#ifdef __x86_64__
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#define L1_PAGETABLE_SHIFT 12
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#define L2_PAGETABLE_SHIFT 21
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#define L3_PAGETABLE_SHIFT 30
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#define L4_PAGETABLE_SHIFT 39
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#define L1_PAGETABLE_ENTRIES 512
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#define L2_PAGETABLE_ENTRIES 512
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#define L3_PAGETABLE_ENTRIES 512
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#define L4_PAGETABLE_ENTRIES 512
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/* These are page-table limitations. Current CPUs support only 40-bit phys. */
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#define PADDR_BITS 52
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#define VADDR_BITS 48
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#define PADDR_MASK ((1UL << PADDR_BITS)-1)
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#define VADDR_MASK ((1UL << VADDR_BITS)-1)
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#define pte_to_mfn(_pte) (((_pte) & (PADDR_MASK&PAGE_MASK)) >> PAGE_SHIFT)
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/* Given a virtual address, get an entry offset into a page table. */
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#define l1_table_offset(_a) \
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(((_a) >> L1_PAGETABLE_SHIFT) & (L1_PAGETABLE_ENTRIES - 1))
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#define l2_table_offset(_a) \
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(((_a) >> L2_PAGETABLE_SHIFT) & (L2_PAGETABLE_ENTRIES - 1))
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#define l3_table_offset(_a) \
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(((_a) >> L3_PAGETABLE_SHIFT) & (L3_PAGETABLE_ENTRIES - 1))
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#define l4_table_offset(_a) \
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(((_a) >> L4_PAGETABLE_SHIFT) & (L4_PAGETABLE_ENTRIES - 1))
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#endif
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#define _PAGE_PRESENT 0x001UL
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#define _PAGE_RW 0x002UL
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#define _PAGE_USER 0x004UL
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#define _PAGE_PWT 0x008UL
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#define _PAGE_PCD 0x010UL
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#define _PAGE_ACCESSED 0x020UL
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#define _PAGE_DIRTY 0x040UL
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#define _PAGE_PAT 0x080UL
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#define _PAGE_PSE 0x080UL
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#define _PAGE_GLOBAL 0x100UL
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#define PAGE_SHIFT 12
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#define PAGE_SIZE (1UL << PAGE_SHIFT)
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#define PAGE_MASK (~(PAGE_SIZE-1))
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#define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT)
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#define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
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#define PFN_PHYS(x) ((x) << PAGE_SHIFT)
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/* to align the pointer to the (next) page boundary */
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#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)
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extern unsigned long *phys_to_machine_mapping;
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#define pfn_to_mfn(_pfn) (phys_to_machine_mapping[(_pfn)])
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#define mfn_to_pfn(_mfn) (machine_to_phys_mapping[(_mfn)])
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static __inline__ unsigned long phys_to_machine(unsigned long phys)
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{
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unsigned long machine = pfn_to_mfn(phys >> PAGE_SHIFT);
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machine = (machine << PAGE_SHIFT) | (phys & ~PAGE_MASK);
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return machine;
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}
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static __inline__ unsigned long machine_to_phys(unsigned long machine)
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{
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unsigned long phys = mfn_to_pfn(machine >> PAGE_SHIFT);
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phys = (phys << PAGE_SHIFT) | (machine & ~PAGE_MASK);
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return phys;
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}
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#ifdef __x86_64__
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#define VIRT_START 0xFFFFFFFF00000000UL
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#else
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#define VIRT_START 0xC0000000UL
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#endif
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#define to_phys(x) ((unsigned long)(x)-VIRT_START)
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#define to_virt(x) ((void *)((unsigned long)(x)+VIRT_START))
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#define __va to_virt
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#define __pa to_phys
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void init_mm(void);
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unsigned long alloc_pages(int order);
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#endif /* _MM_H_ */
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