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Roger Pau Monné
5de961d9c0
When using global pages a full tlb flush can only be performed by toggling the PGE bit in CR4, which is usually quite expensive in terms of performance when running virtualized. This is specially relevant on AMD or Hygon hardware, which doesn't have the ability to do selective CR4 trapping, but can also be relevant on e.g. Intel if the underlying hypervisor also traps accesses to the PGE CR4 bit. In order to avoid this performance penalty, do not use global pages when running virtualized on AMD or Hygon hardware. A command line option 'global-pages' is provided in order to allow the user to select whether global pages will be enabled for PV guests. The above figures are from a PV shim running on AMD hardware with 32 vCPUs: PGE enabled, x2APIC mode: (XEN) Global lock flush_lock: addr=ffff82d0804b01c0, lockval=1adb1adb, not locked (XEN) lock:1841883(1375128998543), block:1658716(10193054890781) Average lock time: 746588ns Average block time: 6145147ns PGE disabled, x2APIC mode: (XEN) Global lock flush_lock: addr=ffff82d0804af1c0, lockval=a8bfa8bf, not locked (XEN) lock:2730175(657505389886), block:2039716(2963768247738) Average lock time: 240829ns Average block time: 1453029ns As seen from the above figures the lock and block time of the flush lock is reduced to approximately 1/3 of the original value. Note that XEN_MINIMAL_CR4 and mmu_cr4_features are not modified, and thus global pages are left enabled for the hypervisor. This is not an issue because the code to switch the control registers (cr3 and cr4) already takes into account such situation and performs the necessary flushes. The same already happens when using XPTI or PCIDE, as the guest cr4 doesn't have global pages enabled in that case either. Also note that the suspend and resume code is correct in writing mmu_cr4_features into cr4 on resume, since that's the cr4 used by the idle vCPU which is the context used by the suspend and resume routine. Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com>
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