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arun.sharma@intel.com[kaf24]
382ed0e218
[PATCH] Infrastructure for interrupt handling. Infrastructure for interrupt handling. - support interruptibility - handle interrupt window exiting control appropriately - Add ioapic device models imported from Bochs under LGPL - generalize the interrupt architecture to support both PIC/APIC This patch is necessary to fix several bugs on 32 bit VMX and prepares the ground for adding a local APIC device model in the hypervisor. Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com> Signed-off-by: Eddie Dong <eddie.dong@intel.com> Signed-off-by: Arun Sharma <arun.sharma@intel.com>
705 lines
19 KiB
C
705 lines
19 KiB
C
/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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//
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#include "vl.h"
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#include "ioapic.h"
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#ifdef __OS
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#undef __OS
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#endif
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#ifdef __i386__
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#define __OS "l"
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#else
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#define __OS "q"
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#endif
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#define ADDR (*(volatile long *) addr)
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#ifdef IOAPIC_DEBUG
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#define IOAPIC_LOG(a...) fprintf(logfile, ##a)
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#else
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#define IOAPIC_LOG(a...)
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#endif
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static IOAPICState *ioapic;
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#define IOAPIC_ERR(a...) fprintf(logfile, ##a)
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static __inline__ int test_and_set_bit(long nr, volatile void * addr)
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{
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long oldbit;
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__asm__ __volatile__(
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"bts"__OS" %2,%1\n\tsbb"__OS" %0,%0"
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:"=r" (oldbit),"=m" (ADDR)
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:"Ir" (nr) : "memory");
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return oldbit;
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}
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static __inline__ int test_and_clear_bit(long nr, volatile void * addr)
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{
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long oldbit;
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__asm__ __volatile__( LOCK_PREFIX
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"btr"__OS" %2,%1\n\tsbb"__OS" %0,%0"
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:"=r" (oldbit),"=m" (ADDR)
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:"dIr" (nr) : "memory");
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return oldbit;
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}
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static __inline__ void clear_bit(long nr, volatile void * addr)
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{
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__asm__ __volatile__(
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"btr"__OS" %1,%0"
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:"=m" (ADDR)
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:"Ir" (nr));
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}
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static inline
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void get_shareinfo_apic_msg(vlapic_info *share_info){
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while(test_and_set_bit(VL_STATE_MSG_LOCK, &share_info->vl_state)){};
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}
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static inline
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void put_shareinfo_apic_msg(vlapic_info *share_info){
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clear_bit(VL_STATE_MSG_LOCK, &share_info->vl_state);
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}
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static inline
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void get_shareinfo_eoi(vlapic_info *share_info){
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while(test_and_set_bit(VL_STATE_EOI_LOCK, &share_info->vl_state)){};
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}
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static inline
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void put_shareinfo_eoi(vlapic_info *share_info){
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clear_bit(VL_STATE_EOI_LOCK, &share_info->vl_state);
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}
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static inline
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void get_shareinfo_ext(vlapic_info *share_info){
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while(test_and_set_bit(VL_STATE_EXT_LOCK, &share_info->vl_state));
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}
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static inline
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void put_shareinfo_ext(vlapic_info *share_info){
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clear_bit(VL_STATE_EXT_LOCK, &share_info->vl_state);
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}
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static __inline__ int test_bit(int nr, uint32_t value){
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return value & (1 << nr);
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}
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static void ioapic_enable(IOAPICState *s, uint8_t enable)
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{
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if (!enable ^ IOAPICEnabled(s)) return;
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if(enable)
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s->flags |= IOAPIC_ENABLE_FLAG;
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else
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s->flags &= ~IOAPIC_ENABLE_FLAG;
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}
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#ifdef IOAPIC_DEBUG
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static void
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ioapic_dump_redir(IOAPICState *s, uint8_t entry)
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{
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if (!s)
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return;
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RedirStatus redir = s->redirtbl[entry];
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fprintf(logfile, "entry %x: "
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"vector %x deliver_mod %x destmode %x delivestatus %x "
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"polarity %x remote_irr %x trigmod %x mask %x dest_id %x\n",
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entry,
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redir.RedirForm.vector, redir.RedirForm.deliver_mode,
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redir.RedirForm.destmode, redir.RedirForm.delivestatus,
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redir.RedirForm.polarity, redir.RedirForm.remoteirr,
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redir.RedirForm.trigmod, redir.RedirForm.mask,
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redir.RedirForm.dest_id);
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}
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static void
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ioapic_dump_shareinfo(IOAPICState *s , int number)
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{
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if (!s || !s->lapic_info[number])
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return;
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vlapic_info *m = s->lapic_info[number];
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IOAPIC_LOG("lapic_info %x : "
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"vl_lapic_id %x vl_logical_dest %x vl_dest_format %x vl_arb_id %x\n",
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number, m->vl_lapic_id, m->vl_logical_dest, m->vl_dest_format, m->vl_arb_id );
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}
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#endif
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static void
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ioapic_save(QEMUFile* f,void* opaque)
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{
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IOAPIC_ERR("no implementation for ioapic_save\n");
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}
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static
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int ioapic_load(QEMUFile* f,void* opaque,int version_id)
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{
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IOAPIC_ERR("no implementation for ioapic_load\n");
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return 0;
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}
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uint32_t
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ioapic_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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IOAPIC_ERR("ioapic_mem_readb\n");
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return 0;
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}
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uint32_t
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ioapic_mem_readw(void *opaque, target_phys_addr_t addr)
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{
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IOAPIC_ERR("ioapic_mem_readw\n");
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return 0;
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}
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static
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void ioapic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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IOAPIC_ERR("ioapic_mem_writeb\n");
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}
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static
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void ioapic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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IOAPIC_ERR("ioapic_mem_writew\n");
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}
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static
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uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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unsigned short ioregsel;
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IOAPICState *s = opaque;
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uint32_t result = 0;
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uint32_t redir_index = 0;
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uint64_t redir_content = 0;
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IOAPIC_LOG("apic_mem_readl addr %x\n", addr);
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if (!s){
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IOAPIC_ERR("null pointer for apic_mem_readl\n");
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return result;
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}
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addr &= 0xff;
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if(addr == 0x00){
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result = s->ioregsel;
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return result;
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}else if (addr != 0x10){
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IOAPIC_ERR("apic_mem_readl address error\n");
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return result;
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}
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ioregsel = s->ioregsel;
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switch (ioregsel){
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case IOAPIC_REG_APIC_ID:
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result = ((s->id & 0xf) << 24);
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break;
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case IOAPIC_REG_VERSION:
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result = ((((IOAPIC_NUM_PINS-1) & 0xff) << 16)
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| (IOAPIC_VERSION_ID & 0x0f));
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break;
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case IOAPIC_REG_ARB_ID:
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//FIXME
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result = ((s->id & 0xf) << 24);
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break;
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default:
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redir_index = (ioregsel - 0x10) >> 1;
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if (redir_index >= 0 && redir_index < IOAPIC_NUM_PINS){
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redir_content = s->redirtbl[redir_index].value;
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result = (ioregsel & 0x1)?
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(redir_content >> 32) & 0xffffffff :
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redir_content & 0xffffffff;
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}else{
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IOAPIC_ERR(
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"upic_mem_readl:undefined ioregsel %x\n",
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ioregsel);
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}
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}
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return result;
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}
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static
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void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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IOAPICState *s = opaque;
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uint32_t redir_index = 0;
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uint64_t redir_content;
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IOAPIC_LOG("apic_mem_writel addr %x val %x\n", addr, val);
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if (!s){
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IOAPIC_ERR("apic_mem_writel: null opaque\n");
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return;
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}
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addr &= 0xff;
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if (addr == 0x00){
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s->ioregsel = val;
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return;
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}else if (addr != 0x10){
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IOAPIC_ERR("apic_mem_writel: unsupported address\n");
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}
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switch (s->ioregsel){
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case IOAPIC_REG_APIC_ID:
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s->id = (val >> 24) & 0xf;
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break;
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case IOAPIC_REG_VERSION:
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IOAPIC_ERR("apic_mem_writel: version register read only\n");
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break;
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case IOAPIC_REG_ARB_ID:
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s->arb_id = val;
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break;
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default:
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redir_index = (s->ioregsel - 0x10) >> 1;
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// IOAPIC_LOG("apic_mem_write: change redir :index %x before %lx, val %x\n", redir_index, s->redirtbl[redir_index].value, val);
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if (redir_index >= 0 && redir_index < IOAPIC_NUM_PINS){
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redir_content = s->redirtbl[redir_index].value;
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if (s->ioregsel & 0x1)
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redir_content = (((uint64_t)val & 0xffffffff) << 32) | (redir_content & 0xffffffff);
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else
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redir_content = ((redir_content >> 32) << 32) | (val & 0xffffffff);
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s->redirtbl[redir_index].value = redir_content;
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}else {
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IOAPIC_ERR("apic_mem_writel: error register\n");
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}
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//IOAPIC_LOG("after value is %lx\n", s->redirtbl[redir_index].value);
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}
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}
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static CPUReadMemoryFunc *ioapic_mem_read[3] = {
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ioapic_mem_readb,
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ioapic_mem_readw,
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ioapic_mem_readl,
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};
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static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
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ioapic_mem_writeb,
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ioapic_mem_writew,
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ioapic_mem_writel,
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};
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void
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IOAPICReset(IOAPICState *s)
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{
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int i;
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if (!s)
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return ;
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memset(s, 0, sizeof(IOAPICState));
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for (i = 0; i < IOAPIC_NUM_PINS; i++)
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s->redirtbl[i].RedirForm.mask = 0x1;
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// IOAPIC_LOG("after Reset %lx\n", s->redirtbl[0].value);
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}
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void
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ioapic_update_config(IOAPICState *s, unsigned long address, uint8_t enable)
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{
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int ioapic_mem;
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if (!s)
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return;
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ioapic_enable(s, enable);
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if (address != s->base_address){
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ioapic_mem = cpu_register_io_memory(0, ioapic_mem_read, ioapic_mem_write, s);
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cpu_register_physical_memory(address, IOAPIC_MEM_LENGTH, ioapic_mem);
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s->base_address = ioapic_mem;
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}
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}
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#define direct_intr(mode) \
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(mode == VLAPIC_DELIV_MODE_SMI || \
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mode == VLAPIC_DELIV_MODE_NMI || \
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mode == VLAPIC_DELIV_MODE_INIT ||\
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mode == VLAPIC_DELIV_MODE_STARTUP)
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int
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ioapic_inj_irq(IOAPICState *s, uint8_t dest, uint8_t vector, uint8_t trig_mode, uint8_t delivery_mode)
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{
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int msg_count;
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if (!s || !s->lapic_info[dest]){
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IOAPIC_ERR("ioapic_inj_irq NULL parameter\n");
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return 0;
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}
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IOAPIC_LOG("ioapic_inj_irq %d , trig %d delive mode %d\n",
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vector, trig_mode, delivery_mode);
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switch(delivery_mode){
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case VLAPIC_DELIV_MODE_FIXED:
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case VLAPIC_DELIV_MODE_LPRI:
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get_shareinfo_apic_msg(s->lapic_info[dest]);
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msg_count = s->lapic_info[dest]->apic_msg_count;
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s->lapic_info[dest]->vl_apic_msg[msg_count].deliv_mode = delivery_mode;
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s->lapic_info[dest]->vl_apic_msg[msg_count].level = trig_mode;
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s->lapic_info[dest]->vl_apic_msg[msg_count].vector = vector;
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s->lapic_info[dest]->vl_apic_msg[msg_count].vector = vector;
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s->lapic_info[dest]->apic_msg_count ++;
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put_shareinfo_apic_msg(s->lapic_info[dest]);
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break;
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case VLAPIC_DELIV_MODE_EXT:
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/* get_shareinfo_ext(s->lapic_info[dest]);
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test_and_set_bit(vector, &s->lapic_info[dest]->vl_ext_intr[0]);
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put_shareinfo_ext(s->lapic_info[dest]);*/
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IOAPIC_ERR("<ioapic_inj_irq> Ext interrupt\n");
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return 0;
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default:
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IOAPIC_ERR("<ioapic_inj_irq> error delivery mode\n");
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break;
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}
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return 1;
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}
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int
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ioapic_match_logical_addr(IOAPICState *s, int number, uint8_t address)
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{
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if(!s || !s->lapic_info[number]){
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IOAPIC_ERR("ioapic_match_logical_addr NULL parameter: "
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"number: %i s %p address %x\n",
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number, s, address);
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return 0;
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}
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IOAPIC_LOG("ioapic_match_logical_addr number %i address %x\n",
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number, address);
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if (((s->lapic_info[number]->vl_dest_format >> 28 ) & 0xf) != 0xf) {
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IOAPIC_ERR("ioapic_match_logical_addr: cluster model not implemented still%x"
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,s->lapic_info[number]->vl_dest_format);
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#ifdef IOAPIC_DEBUG
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ioapic_dump_shareinfo(s, number);
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#endif
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return 0;
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}
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return ((address & ((s->lapic_info[number]->vl_logical_dest >> 24) & 0xff)) != 0);
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}
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int
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ioapic_get_apr_lowpri(IOAPICState *s, int number)
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{
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if(!s || !s->lapic_info[number]){
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IOAPIC_ERR("ioapic_get_apr_lowpri NULL parameter\n");
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return 0;
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}
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return s->lapic_info[number]->vl_arb_id;
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}
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uint32_t
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ioapic_get_delivery_bitmask(IOAPICState *s,
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uint8_t dest, uint8_t dest_mode, uint8_t vector, uint8_t delivery_mode)
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{
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uint32_t mask = 0;
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int low_priority = 256, selected = -1, i;
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fprintf(logfile, "<ioapic_get_delivery_bitmask>: dest %d dest_mode %d"
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"vector %d del_mode %d, lapic_count %d\n",
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dest, dest_mode, vector, delivery_mode, s->lapic_count);
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if (!s) return mask;
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if (dest_mode == 0) { //Physical mode
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if ((dest < s->lapic_count) && s->lapic_info[dest])
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mask = 1 << dest;
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}
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else {
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/* logical destination. call match_logical_addr for each APIC. */
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if (dest == 0) return 0;
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for (i=0; i< s->lapic_count; i++) {
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//FIXME focus one, since no such issue on IPF, shoudl we add it?
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if ( s->lapic_info[i] && ioapic_match_logical_addr(s, i, dest)){
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if (delivery_mode != APIC_DM_LOWPRI)
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mask |= (1<<i);
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else {
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if (low_priority > ioapic_get_apr_lowpri(s, i)){
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low_priority = ioapic_get_apr_lowpri(s, i);
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selected = i;
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}
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fprintf(logfile, "%d low_priority %d apr %d select %d\n",
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i, low_priority, ioapic_get_apr_lowpri(s, i), selected);
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}
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}
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}
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if (delivery_mode == APIC_DM_LOWPRI && (selected != -1))
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mask |= (1<< selected);
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}
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return mask;
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}
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void
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ioapic_deliver(IOAPICState *s, int irqno){
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uint8_t dest = s->redirtbl[irqno].RedirForm.dest_id;
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uint8_t dest_mode = s->redirtbl[irqno].RedirForm.destmode;
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uint8_t delivery_mode = s->redirtbl[irqno].RedirForm.deliver_mode;
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uint8_t vector = s->redirtbl[irqno].RedirForm.vector;
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uint8_t trig_mode = s->redirtbl[irqno].RedirForm.trigmod;
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uint8_t bit;
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uint32_t deliver_bitmask;
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IOAPIC_LOG("IOAPIC deliver: "
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"dest %x dest_mode %x delivery_mode %x vector %x trig_mode %x\n",
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dest, dest_mode, delivery_mode, vector, trig_mode);
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deliver_bitmask =
|
|
ioapic_get_delivery_bitmask(s, dest, dest_mode, vector, delivery_mode);
|
|
|
|
IOAPIC_LOG("ioapic_get_delivery_bitmask return %x\n", deliver_bitmask);
|
|
if (!deliver_bitmask){
|
|
IOAPIC_ERR("Ioapic deliver, no target on destination\n");
|
|
return ;
|
|
}
|
|
|
|
switch (delivery_mode){
|
|
case VLAPIC_DELIV_MODE_FIXED:
|
|
case VLAPIC_DELIV_MODE_LPRI:
|
|
case VLAPIC_DELIV_MODE_EXT:
|
|
break;
|
|
case VLAPIC_DELIV_MODE_SMI:
|
|
case VLAPIC_DELIV_MODE_NMI:
|
|
case VLAPIC_DELIV_MODE_INIT:
|
|
case VLAPIC_DELIV_MODE_STARTUP:
|
|
default:
|
|
IOAPIC_ERR("Not support delivey mode %d\n", delivery_mode);
|
|
return ;
|
|
}
|
|
|
|
for (bit = 0; bit < s->lapic_count; bit++){
|
|
if (deliver_bitmask & (1 << bit)){
|
|
if (s->lapic_info[bit]){
|
|
ioapic_inj_irq(s, bit, vector, trig_mode, delivery_mode);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
static inline int __fls(u32 word)
|
|
{
|
|
int bit;
|
|
__asm__("bsrl %1,%0"
|
|
:"=r" (bit)
|
|
:"rm" (word));
|
|
return word ? bit : -1;
|
|
}
|
|
|
|
#if 0
|
|
static __inline__ int find_highest_bit(unsigned long *data, int length){
|
|
while(length && !data[--length]);
|
|
return __fls(data[length]) + 32 * length;
|
|
}
|
|
#endif
|
|
int
|
|
ioapic_get_highest_irq(IOAPICState *s){
|
|
uint32_t irqs;
|
|
if (!s)
|
|
return -1;
|
|
irqs = s->irr & ~s->isr;
|
|
return __fls(irqs);
|
|
}
|
|
|
|
|
|
void
|
|
service_ioapic(IOAPICState *s){
|
|
int irqno;
|
|
|
|
while((irqno = ioapic_get_highest_irq(s)) != -1){
|
|
IOAPIC_LOG("service_ioapic: highest irqno %x\n", irqno);
|
|
|
|
if (!s->redirtbl[irqno].RedirForm.mask)
|
|
ioapic_deliver(s, irqno);
|
|
|
|
if (s->redirtbl[irqno].RedirForm.trigmod == IOAPIC_LEVEL_TRIGGER){
|
|
s->isr |= (1 << irqno);
|
|
}
|
|
// clear_bit(irqno, &s->irr);
|
|
s->irr &= ~(1 << irqno);
|
|
}
|
|
}
|
|
|
|
void
|
|
ioapic_update_irq(IOAPICState *s)
|
|
{
|
|
s->INTR = 1;
|
|
}
|
|
|
|
void
|
|
ioapic_set_irq(IOAPICState *s, int irq, int level)
|
|
{
|
|
IOAPIC_LOG("ioapic_set_irq %x %x\n", irq, level);
|
|
|
|
/* Timer interrupt implemented on HV side */
|
|
if(irq == 0x0) return;
|
|
if (!s){
|
|
fprintf(logfile, "ioapic_set_irq null parameter\n");
|
|
return;
|
|
}
|
|
if (!IOAPICEnabled(s) || s->redirtbl[irq].RedirForm.mask)
|
|
return;
|
|
#ifdef IOAPIC_DEBUG
|
|
ioapic_dump_redir(s, irq);
|
|
#endif
|
|
if (irq >= 0 && irq < IOAPIC_NUM_PINS){
|
|
uint32_t bit = 1 << irq;
|
|
if (s->redirtbl[irq].RedirForm.trigmod == IOAPIC_LEVEL_TRIGGER){
|
|
if(level)
|
|
s->irr |= bit;
|
|
else
|
|
s->irr &= ~bit;
|
|
}else{
|
|
if(level)
|
|
/* XXX No irr clear for edge interrupt */
|
|
s->irr |= bit;
|
|
}
|
|
}
|
|
|
|
ioapic_update_irq(s);
|
|
}
|
|
|
|
void
|
|
ioapic_legacy_irq(int irq, int level)
|
|
{
|
|
ioapic_set_irq(ioapic, irq, level);
|
|
}
|
|
|
|
static inline int find_highest_bit(u32 *data, int length){
|
|
while(length && !data[--length]);
|
|
return __fls(data[length]) + 32 * length;
|
|
}
|
|
|
|
int
|
|
get_redir_num(IOAPICState *s, int vector){
|
|
int i = 0;
|
|
if(!s){
|
|
IOAPIC_ERR("Null parameter for get_redir_num\n");
|
|
return -1;
|
|
}
|
|
for(; i < IOAPIC_NUM_PINS-1; i++){
|
|
if (s->redirtbl[i].RedirForm.vector == vector)
|
|
return i;
|
|
}
|
|
return -1;
|
|
}
|
|
|
|
void
|
|
ioapic_update_EOI()
|
|
{
|
|
int i = 0;
|
|
uint32_t isr_info ;
|
|
uint32_t vector;
|
|
IOAPICState *s = ioapic;
|
|
|
|
isr_info = s->isr;
|
|
|
|
for (i = 0; i < s->lapic_count; i++){
|
|
if (!s->lapic_info[i] ||
|
|
!test_bit(VL_STATE_EOI, s->lapic_info[i]->vl_state))
|
|
continue;
|
|
get_shareinfo_eoi(s->lapic_info[i]);
|
|
while((vector = find_highest_bit((unsigned int *)&s->lapic_info[i]->vl_eoi[0],VLAPIC_INT_COUNT_32)) != -1){
|
|
int redir_num;
|
|
if ((redir_num = get_redir_num(s, vector)) == -1){
|
|
IOAPIC_ERR("Can't find redir item for %d EOI \n", vector);
|
|
continue;
|
|
}
|
|
if (!test_and_clear_bit(redir_num, &s->isr)){
|
|
IOAPIC_ERR("redir %d not set for %d EOI\n", redir_num, vector);
|
|
continue;
|
|
}
|
|
clear_bit(vector, &s->lapic_info[i]->vl_eoi[0]);
|
|
}
|
|
clear_bit(VL_STATE_EOI, &s->lapic_info[i]->vl_state);
|
|
put_shareinfo_eoi(s->lapic_info[i]);
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
ioapic_init_apic_info(IOAPICState *s)
|
|
{
|
|
#ifdef IOAPIC_DEBUG
|
|
fprintf(logfile, "ioapic_init_apic_info\n");
|
|
if (!s)
|
|
return;
|
|
#endif
|
|
|
|
#if 0
|
|
if (!vio || !(vio->vl_number)){
|
|
fprintf(logfile, "null vio or o vl number\n");
|
|
return;
|
|
}
|
|
|
|
for (i = 0; i < MAX_LAPIC_NUM; i++) s->lapic_info[i] = NULL;
|
|
|
|
s->lapic_count = vio->vl_number;
|
|
for (i = 0; i < vio->vl_number; i++)
|
|
s->lapic_info[i] = vio->vl_info + i;
|
|
#endif
|
|
|
|
}
|
|
|
|
void
|
|
ioapic_intack(IOAPICState *s)
|
|
{
|
|
#ifdef IOAPIC_DEBUG
|
|
if (!s){
|
|
fprintf(logfile, "ioapic_intack null parameter\n");
|
|
return;
|
|
}
|
|
#endif
|
|
if (!s) s->INTR = 0;
|
|
}
|
|
|
|
int
|
|
ioapic_has_intr()
|
|
{
|
|
return ioapic->INTR;
|
|
}
|
|
|
|
void
|
|
do_ioapic()
|
|
{
|
|
service_ioapic(ioapic);
|
|
ioapic_intack(ioapic);
|
|
}
|
|
|
|
IOAPICState *
|
|
IOAPICInit( )
|
|
{
|
|
IOAPICState *s;
|
|
|
|
s = qemu_mallocz(sizeof(IOAPICState));
|
|
if (!s){
|
|
fprintf(logfile, "IOAPICInit: malloc failed\n");
|
|
return NULL;
|
|
}
|
|
|
|
IOAPICReset(s);
|
|
ioapic_init_apic_info(s);
|
|
register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
|
|
/* Remove after GFW ready */
|
|
ioapic_update_config(s, 0xfec00000, 1);
|
|
|
|
ioapic = s;
|
|
return s;
|
|
}
|