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arun.sharma@intel.com[kaf24]
382ed0e218
[PATCH] Infrastructure for interrupt handling. Infrastructure for interrupt handling. - support interruptibility - handle interrupt window exiting control appropriately - Add ioapic device models imported from Bochs under LGPL - generalize the interrupt architecture to support both PIC/APIC This patch is necessary to fix several bugs on 32 bit VMX and prepares the ground for adding a local APIC device model in the hypervisor. Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com> Signed-off-by: Eddie Dong <eddie.dong@intel.com> Signed-off-by: Arun Sharma <arun.sharma@intel.com>
129 lines
3.2 KiB
C
129 lines
3.2 KiB
C
/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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//
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// MandrakeSoft S.A.
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// 43, rue d'Aboukir
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// 75002 Paris - France
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// http://www.linux-mandrake.com/
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// http://www.mandrakesoft.com/
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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//
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#ifndef __IOAPIC_H
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#define __IOAPIC_H
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#include "xc.h"
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#include <io/ioreq.h>
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#include <io/vmx_vlapic.h>
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#define IOAPIC_NUM_PINS 24
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#define IOAPIC_VERSION_ID 0x11
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#define IOAPIC_LEVEL_TRIGGER 1
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#define APIC_DM_FIXED 0
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#define APIC_DM_LOWPRI 1
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#ifdef CONFIG_SMP
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#define LOCK_PREFIX "lock ; "
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#else
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#define LOCK_PREFIX ""
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#endif
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#ifdef __I386__
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#define __OS "q"
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#define __OP "r"
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#else
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#define __OS "l" /* Operation Suffix */
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#define __OP "e" /* Operand Prefix */
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#endif
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#define ADDR (*(volatile long *) addr)
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#if 0
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#endif
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extern void *shared_page;
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extern FILE *logfile;
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#ifdef __BIGENDIAN__
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typedef union RedirStatus
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{
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uint64_t value;
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struct {
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uint8_t dest_id;
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uint8_t reserved[4];
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uint8_t reserve:7;
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uint8_t mask:1; /* interrupt mask*/
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uint8_t trigmod:1;
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uint8_t remoteirr:1;
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uint8_t polarity:1;
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uint8_t delivestatus:1;
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uint8_t destmode:1;
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uint8_t deliver_mode:3;
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uint8_t vector;
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}RedirForm;
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}RedirStatus;
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#else
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typedef union RedirStatus
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{
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uint64_t value;
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struct {
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uint8_t vector;
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uint8_t deliver_mode:3;
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uint8_t destmode:1;
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uint8_t delivestatus:1;
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uint8_t polarity:1;
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uint8_t remoteirr:1;
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uint8_t trigmod:1;
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uint8_t mask:1; /* interrupt mask*/
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uint8_t reserve:7;
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uint8_t reserved[4];
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uint8_t dest_id;
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}RedirForm;
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}RedirStatus;
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#endif
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/*
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* IOAPICState stands for a instance of a IOAPIC
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*/
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/* FIXME tmp before working with Local APIC */
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#define IOAPIC_MEM_LENGTH 0x100
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#define IOAPIC_ENABLE_MASK 0x0
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#define IOAPIC_ENABLE_FLAG (1 << IOAPIC_ENABLE_MASK)
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#define MAX_LAPIC_NUM 32
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struct IOAPICState{
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uint32_t INTR;
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uint32_t id;
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uint32_t arb_id;
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uint32_t flags;
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unsigned long base_address;
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uint32_t irr;
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uint32_t isr; /* This is used for level trigger */
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uint8_t vector_irr[256];
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RedirStatus redirtbl[IOAPIC_NUM_PINS];
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uint32_t ioregsel;
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uint32_t lapic_count;
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vlapic_info *lapic_info[MAX_LAPIC_NUM];
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};
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#define IOAPIC_REG_APIC_ID 0x0
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#define IOAPIC_REG_VERSION 0x1
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#define IOAPIC_REG_ARB_ID 0x2
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#define IOAPICEnabled(s) (s->flags & IOAPIC_ENABLE_FLAG)
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typedef struct IOAPICState IOAPICState;
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#endif
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