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rneugeba@wyvis.research.intel-research.net
3bd36ccc50
forward ported James Bulpin's performance counters tool Signed-off-by: michael.fetterman@cl.cam.ac.uk
372 lines
9.2 KiB
Plaintext
372 lines
9.2 KiB
Plaintext
Usage
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=====
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Use either xen-cpuperf, cpuperf-perfcntr as appropriate to the system
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in use.
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To write:
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cpuperf -E <escr> -C <cccr>
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optional: all numbers in base 10 unless specified
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-d Debug mode
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-c <cpu> CPU number
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-t <thread> ESCR thread bits - default is 12 (Thread 0 all rings)
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bit 0: Thread 1 in rings 1,2,3
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bit 1: Thread 1 in ring 0
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bit 2: Thread 0 in rings 1,2,3
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bit 3: Thread 0 in ring 0
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-e <eventsel> Event selection number
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-m <eventmask> Event mask bits
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-T <value> ESCR tag value
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-k Sets CCCR 'compare' bit
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-n Sets CCCR 'complement' bit
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-g Sets CCCR 'edge' bit
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-P <bit> Set the specified bit in MSR_P4_PEBS_ENABLE
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-V <bit> Set the specified bit in MSR_P4_PEBS_MATRIX_VERT
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(-V and -P may be used multiple times to set multiple bits.)
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To read:
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cpuperf -r
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optional: all numbers in base 10 unless specified
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-c <cpu> CPU number
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<cccr> values:
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BPU_CCCR0
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BPU_CCCR1
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BPU_CCCR2
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BPU_CCCR3
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MS_CCCR0
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MS_CCCR1
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MS_CCCR2
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MS_CCCR3
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FLAME_CCCR0
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FLAME_CCCR1
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FLAME_CCCR2
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FLAME_CCCR3
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IQ_CCCR0
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IQ_CCCR1
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IQ_CCCR2
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IQ_CCCR3
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IQ_CCCR4
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IQ_CCCR5
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NONE - do not program any CCCR, used when setting up an ESCR for tagging
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<escr> values:
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BSU_ESCR0
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BSU_ESCR1
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FSB_ESCR0
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FSB_ESCR1
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MOB_ESCR0
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MOB_ESCR1
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PMH_ESCR0
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PMH_ESCR1
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BPU_ESCR0
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BPU_ESCR1
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IS_ESCR0
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IS_ESCR1
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ITLB_ESCR0
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ITLB_ESCR1
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IX_ESCR0
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IX_ESCR1
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MS_ESCR0
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MS_ESCR1
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TBPU_ESCR0
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TBPU_ESCR1
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TC_ESCR0
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TC_ESCR1
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FIRM_ESCR0
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FIRM_ESCR1
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FLAME_ESCR0
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FLAME_ESCR1
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DAC_ESCR0
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DAC_ESCR1
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SAAT_ESCR0
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SAAT_ESCR1
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U2L_ESCR0
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U2L_ESCR1
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CRU_ESCR0
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CRU_ESCR1
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CRU_ESCR2
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CRU_ESCR3
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CRU_ESCR4
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CRU_ESCR5
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IQ_ESCR0
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IQ_ESCR1
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RAT_ESCR0
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RAT_ESCR1
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SSU_ESCR0
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SSU_ESCR1
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ALF_ESCR0
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ALF_ESCR1
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Example configurations
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======================
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Note than in most cases there is a choice of ESCRs and CCCRs for
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each metric although not all combinations are allowed. Each ESCR and
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counter/CCCR can be used only once.
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Mispredicted branches retired
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=============================
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cpuperf -E CRU_ESCR0 -C IQ_CCCR0 -e 3 -m 1
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cpuperf -E CRU_ESCR0 -C IQ_CCCR1 -e 3 -m 1
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cpuperf -E CRU_ESCR0 -C IQ_CCCR4 -e 3 -m 1
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cpuperf -E CRU_ESCR1 -C IQ_CCCR2 -e 3 -m 1
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cpuperf -E CRU_ESCR1 -C IQ_CCCR3 -e 3 -m 1
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cpuperf -E CRU_ESCR1 -C IQ_CCCR5 -e 3 -m 1
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Tracecache misses
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=================
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cpuperf -E BPU_ESCR0 -C BPU_CCCR0 -e 3 -m 1
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cpuperf -E BPU_ESCR0 -C BPU_CCCR1 -e 3 -m 1
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cpuperf -E BPU_ESCR1 -C BPU_CCCR2 -e 3 -m 1
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cpuperf -E BPU_ESCR1 -C BPU_CCCR3 -e 3 -m 1
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I-TLB
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=====
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cpuperf -E ITLB_ESCR0 -C BPU_CCCR0 -e 24
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cpuperf -E ITLB_ESCR0 -C BPU_CCCR1 -e 24
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cpuperf -E ITLB_ESCR1 -C BPU_CCCR2 -e 24
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cpuperf -E ITLB_ESCR1 -C BPU_CCCR3 -e 24
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-m <n> : bit 0 count HITS, bit 1 MISSES, bit 2 uncacheable hit
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e.g. all ITLB misses -m 2
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Load replays
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============
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cpuperf -E MOB_ESCR0 -C BPU_CCCR0 -e 3
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cpuperf -E MOB_ESCR0 -C BPU_CCCR1 -e 3
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cpuperf -E MOB_ESCR1 -C BPU_CCCR2 -e 3
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cpuperf -E MOB_ESCR1 -C BPU_CCCR3 -e 3
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-m <n> : bit mask, replay due to...
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1: unknown store address
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3: unknown store data
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4: partially overlapped data access between LD/ST
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5: unaligned address between LD/ST
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Page walks
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==========
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cpuperf -E PMH_ESCR0 -C BPU_CCCR0 -e 1
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cpuperf -E PMH_ESCR0 -C BPU_CCCR1 -e 1
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cpuperf -E PMH_ESCR1 -C BPU_CCCR2 -e 1
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cpuperf -E PMH_ESCR1 -C BPU_CCCR3 -e 1
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-m <n> : bit 0 counts walks for a D-TLB miss, bit 1 for I-TLB miss
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L2/L3 cache accesses
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====================
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cpuperf -E BSU_ESCR0 -C BPU_CCCR0 -e 12
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cpuperf -E BSU_ESCR0 -C BPU_CCCR1 -e 12
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cpuperf -E BSU_ESCR1 -C BPU_CCCR2 -e 12
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cpuperf -E BSU_ESCR1 -C BPU_CCCR3 -e 12
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-m <n> : where the bit mask is:
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0: Read L2 HITS Shared
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1: Read L2 HITS Exclusive
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2: Read L2 HITS Modified
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3: Read L3 HITS Shared
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4: Read L3 HITS Exclusive
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5: Read L3 HITS Modified
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8: Read L2 MISS
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9: Read L3 MISS
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10: Write L2 MISS
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Front side bus activity
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=======================
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cpuperf -E FSB_ESCR0 -C BPU_CCCR0 -e 23 -k -g
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cpuperf -E FSB_ESCR0 -C BPU_CCCR1 -e 23 -k -g
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cpuperf -E FSB_ESCR1 -C BPU_CCCR2 -e 23 -k -g
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cpuperf -E FSB_ESCR1 -C BPU_CCCR3 -e 23 -k -g
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-m <n> : where the bit mask is for bus events:
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0: DRDY_DRV Processor drives bus
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1: DRDY_OWN Processor reads bus
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2: DRDY_OTHER Data on bus not being sampled by processor
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3: DBSY_DRV Processor reserves bus for driving
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4: DBSY_OWN Other entity reserves bus for sending to processor
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5: DBSY_OTHER Other entity reserves bus for sending elsewhere
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e.g. -m 3 to get cycles bus actually in use.
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Pipeline clear (entire)
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=======================
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cpuperf -E CRU_ESCR2 -C IQ_CCCR0 -e 2
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cpuperf -E CRU_ESCR2 -C IQ_CCCR1 -e 2
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cpuperf -E CRU_ESCR2 -C IQ_CCCR4 -e 2
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cpuperf -E CRU_ESCR3 -C IQ_CCCR2 -e 2
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cpuperf -E CRU_ESCR3 -C IQ_CCCR3 -e 2
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cpuperf -E CRU_ESCR3 -C IQ_CCCR5 -e 2
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-m <n> : bit mask:
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0: counts a portion of cycles while clear (use -g for edge trigger)
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1: counts each time machine clears for memory ordering issues
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2: counts each time machine clears for self modifying code
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Instructions retired
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====================
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cpuperf -E CRU_ESCR0 -C IQ_CCCR0 -e 2
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cpuperf -E CRU_ESCR0 -C IQ_CCCR1 -e 2
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cpuperf -E CRU_ESCR0 -C IQ_CCCR4 -e 2
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cpuperf -E CRU_ESCR1 -C IQ_CCCR2 -e 2
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cpuperf -E CRU_ESCR1 -C IQ_CCCR3 -e 2
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cpuperf -E CRU_ESCR1 -C IQ_CCCR5 -e 2
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-m <n> : bit mask:
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0: counts non-bogus, not tagged instructions
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1: counts non-bogus, tagged instructions
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2: counts bogus, not tagged instructions
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3: counts bogus, tagged instructions
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e.g. -m 3 to count legit retirements
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Uops retired
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============
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cpuperf -E CRU_ESCR0 -C IQ_CCCR0 -e 1
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cpuperf -E CRU_ESCR0 -C IQ_CCCR1 -e 1
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cpuperf -E CRU_ESCR0 -C IQ_CCCR4 -e 1
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cpuperf -E CRU_ESCR1 -C IQ_CCCR2 -e 1
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cpuperf -E CRU_ESCR1 -C IQ_CCCR3 -e 1
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cpuperf -E CRU_ESCR1 -C IQ_CCCR5 -e 1
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-m <n> : bit mask:
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0: Non-bogus
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1: Bogus
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x87 FP uops
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===========
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cpuperf -E FIRM_ESCR0 -C FLAME_CCCR0 -e 4 -m 32768
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cpuperf -E FIRM_ESCR0 -C FLAME_CCCR1 -e 4 -m 32768
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cpuperf -E FIRM_ESCR1 -C FLAME_CCCR2 -e 4 -m 32768
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cpuperf -E FIRM_ESCR1 -C FLAME_CCCR3 -e 4 -m 32768
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Replay tagging mechanism
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========================
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Counts retirement of uops tagged with the replay tagging mechanism
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cpuperf -E CRU_ESCR2 -C IQ_CCCR0 -e 9
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cpuperf -E CRU_ESCR2 -C IQ_CCCR1 -e 9
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cpuperf -E CRU_ESCR2 -C IQ_CCCR4 -e 9
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cpuperf -E CRU_ESCR3 -C IQ_CCCR2 -e 9
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cpuperf -E CRU_ESCR3 -C IQ_CCCR3 -e 9
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cpuperf -E CRU_ESCR3 -C IQ_CCCR5 -e 9
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-m <n> : bit mask:
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0: Non-bogus (set this bit for all events listed below)
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1: Bogus
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Set replay tagging mechanism bits with -P and -V:
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L1 cache load miss retired: -P 0 -P 24 -P 25 -V 0
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L2 cache load miss retired: -P 1 -P 24 -P 25 -V 0 (read manual)
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DTLB load miss retired: -P 2 -P 24 -P 25 -V 0
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DTLB store miss retired: -P 2 -P 24 -P 25 -V 1
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DTLB all miss retired: -P 2 -P 24 -P 25 -V 0 -V 1
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e.g. to count all DTLB misses
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cpuperf -E CRU_ESCR2 -C IQ_CCCR0 -e 9 -m 1 P 2 -P 24 -P 25 -V 0 -V 1
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Front end event
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===============
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To count tagged uops:
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cpuperf -E CRU_ESCR2 -C IQ_CCCR0 -e 8
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cpuperf -E CRU_ESCR2 -C IQ_CCCR1 -e 8
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cpuperf -E CRU_ESCR2 -C IQ_CCCR4 -e 8
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cpuperf -E CRU_ESCR3 -C IQ_CCCR2 -e 8
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cpuperf -E CRU_ESCR3 -C IQ_CCCR3 -e 8
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cpuperf -E CRU_ESCR3 -C IQ_CCCR5 -e 8
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-m <n> : bit 0 for non-bogus uops, bit 1 for bogus uops
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Must have another ESCR programmed to tag uops as required
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cpuperf -E RAT_ESCR0 -C NONE -e 2
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cpuperf -E RAT_ESCR1 -C NONE -e 2
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-m <n> : bit 1 for LOADs, bit 2 for STOREs
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An example set of counters
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===========================
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# instructions retired
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cpuperf -E CRU_ESCR0 -C IQ_CCCR0 -e 2 -m 3
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# trace cache misses
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cpuperf -E BPU_ESCR0 -C BPU_CCCR0 -e 3 -m 1
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# L1 D cache misses (load misses retired)
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cpuperf -E CRU_ESCR2 -C IQ_CCCR1 -e 9 -m 1 -P 0 -P 24 -P 25 -V 0
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# L2 misses (load and store)
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cpuperf -E BSU_ESCR0 -C BPU_CCCR1 -e 12 -m 1280
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# I-TLB misses
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cpuperf -E ITLB_ESCR1 -C BPU_CCCR2 -e 24 -m 2
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# D-TLB misses (as PT walks)
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cpuperf -E PMH_ESCR1 -C BPU_CCCR3 -e 1 -m 1
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# Other 'bonus' counters would be:
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# number of loads executed - need both command lines
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cpuperf -E RAT_ESCR0 -C NONE -e 2 -m 2
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cpuperf -E CRU_ESCR3 -C IQ_CCCR3 -e 8 -m 3
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# number of mispredicted branches
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cpuperf -E CRU_ESCR1 -C IQ_CCCR2 -e 3 -m 1
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# x87 FP uOps
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cpuperf -E FIRM_ESCR0 -C FLAME_CCCR0 -e 4 -m 32768
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The above has counter assignments
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0 Trace cache misses
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1 L2 Misses
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2 I-TLB misses
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3 D-TLB misses
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4
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5
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6
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7
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8 x87 FP uOps
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9
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10
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11
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12 Instructions retired
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13 L1 D cache misses
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14 Mispredicted branches
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15 Loads executed
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17
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Counting instructions retired on each logical CPU
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=================================================
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cpuperf -E CRU_ESCR0 -C IQ_CCCR0 -e 2 -m 3 -t 12
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cpuperf -E CRU_ESCR1 -C IQ_CCCR2 -e 2 -m 3 -t 3
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Cannot count mispred branches as well due to CRU_ESCR1 use.
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