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kaf24@firebug.cl.cam.ac.uk
fc1bbeb091
From: Kaleb Pederson Signed-off-by: Keir Fraser <keir@xensource.com>
119 lines
3.2 KiB
Plaintext
119 lines
3.2 KiB
Plaintext
.TH XENTRACE 8 "11 March 2004" "Xen domain 0 utils"
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.SH NAME
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xentrace \- capture Xen trace buffer data
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.SH SYNOPSIS
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.B xentrace
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[
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.I OPTIONS
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] [
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.I FILE
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]
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.SH DESCRIPTION
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.B xentrace
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is used to capture trace buffer data from Xen. The data is
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output in the following binary format (host endian):
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.PP
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CPU(uint) TSC(u64) EVENT(u32) D1 D2 D3 D4 D5 (all u32)
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.PP
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Where CPU is the processor number, TSC is the record's timestamp
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(the value of the CPU cycle counter), EVENT is the event ID and
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D1...D5 are the trace data.
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Data is dumped onto the standard output (which must not be a TTY) or a
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\fIFILE\fP specified on the command line.
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The output should be parsed using the tool xentrace_format, which can
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produce human-readable output in ASCII format.
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.SS Options
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.TP
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.B -t, --log-thresh=l
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set the threshold number, l, of new records required to trigger a write of
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all new records to the output
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.TP
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.B -s, --poll-sleep=p
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set the time, p, (in milliseconds) to sleep between polling the buffers
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for new data.
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.TP
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.B -c, --cpu-mask=c
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set cpu-mask
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.TP
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.B -e, --evt-mask=e
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set evt-mask
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.TP
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.B -?, --help
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Give this help list
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.TP
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.B --usage
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Give a short usage message
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.TP
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.B -V, --version
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Print program version
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.SS Event Classes (Masks)
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The following event classes (masks) can be used to filter the events being
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gathered by xentrace:
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.PP
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\fIID\fP \fIDescription\fP
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.PP
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0x0001f000 TRC_GEN
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0x0002f000 TRC_SCHED
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0x0004f000 TRC_DOM0OP
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0x0008f000 TRC_VMX
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0x000af000 TRC_MEM
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0xfffff000 TRC_ALL
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.SS Event Subclasses (More Masks)
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The following event subclasses (masks) can also be used to filter the events being
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gathered by xentrace:
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.PP
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\fIID\fP \fIDescription\fP
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.PP
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0x00081000 TRC_VMXEXIT
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0x00082000 TRC_VMXTIMER
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0x00084000 TRC_VMXINT
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0x00088000 TRC_VMXIO
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.SS Events
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.B xentrace
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collects the following events from the trace buffer:
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.PP
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\fIID\fP \fIDescription\fP
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.PP
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0x0002f001 TRC_SCHED_DOM_ADD
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0x0002f002 TRC_SCHED_DOM_REM
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0x0002f003 TRC_SCHED_SLEEP
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0x0002f004 TRC_SCHED_WAKE
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0x0002f005 TRC_SCHED_YIELD
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0x0002f006 TRC_SCHED_BLOCK
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0x0002f007 TRC_SCHED_SHUTDOWN
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0x0002f008 TRC_SCHED_CTL
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0x0002f009 TRC_SCHED_ADJDOM
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0x0002f010 TRC_SCHED_SWITCH
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0x0002f011 TRC_SCHED_S_TIMER_FN
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0x0002f012 TRC_SCHED_T_TIMER_FN
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0x0002f013 TRC_SCHED_DOM_TIMER_FN
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0x0002f014 TRC_SCHED_SWITCH_INFPREV
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0x0002f015 TRC_SCHED_SWITCH_INFNEXT
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0x000af001 TRC_MEM_PAGE_GRANT_MAP
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0x000af002 TRC_MEM_PAGE_GRANT_UNMAP
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0x000af003 TRC_MEM_PAGE_GRANT_TRANSFER
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0x00081001 TRC_VMX_VMEXIT
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0x00081002 TRC_VMX_VMENTRY
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0x00082001 TRC_VMX_TIMER_INTR
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0x00084001 TRC_VMX_INT
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.PP
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.SH AUTHOR
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Mark A. Williamson <mark.a.williamson@intel.com>
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.SH "SEE ALSO"
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xentrace_cpuinfo(1), xentrace_format(1)
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