Roger Pau Monne 92666fdd6e tools/pvh: set coherent MTRR state for all vCPUs ...

Instead of just doing it for the BSP. This requires storing the
maximum number of possible vCPUs in xc_dom_image.

This has been a latent bug so far because PVH doesn't yet support
pci-passthrough, so the effective memory cache attribute is forced to
WB by the hypervisor. Note also that even without this in place vCPU#0
is preferred in certain scenarios in order to calculate the memory
cache attributes.

Reported-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>

2018-10-11 09:42:38 +01:00

..

xc_dom.h

tools/pvh: set coherent MTRR state for all vCPUs

2018-10-11 09:42:38 +01:00

xenctrl_compat.h

x86/domctl: remove XEN_DOMCTL_pin_mem_cacheattr

2018-01-25 12:26:55 +01:00

xenctrl.h

x86/altp2m: Add a hvmop for querying the suppress #VE bit

2018-09-19 18:07:52 +01:00

xenguest.h

tools/libxc: Fix domid parameter types

2017-10-11 12:20:17 +01:00