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Oleksii Kurochko
b3d5fad63a
Svpbmt extension is necessary for chaning the memory type for a page contains
a combination of attributes that indicate the cacheability, idempotency,
and ordering properties for access to that page.
As a part of the patch the following is introduced:
- Svpbmt memory type defintions: PTE_PBMT_{NOCACHE,IO}.
- PAGE_HYPERVISOR_{NOCACHE,WC}.
- RISCV_ISA_EXT_svpbmt and add a check in runtime that Svpbmt is
supported by platform.
- Update riscv/booting.txt with information about Svpbmt.
- Update logic of pt_update_entry() to take into account PBMT bits.
Use 'unsigned long' for pte_attr_t as PBMT bits are 61 and 62 and it doesn't
fit into 'unsigned int'. Also, update function prototypes which uses
'unsigned int' for flags/attibutes.
Enable Svpbmt for testing in QEMU as it is now mandatory for Xen work.
Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
25 lines
1.0 KiB
Plaintext
25 lines
1.0 KiB
Plaintext
System requirements
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===================
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The following extensions are expected to be supported by a system on which
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Xen is run:
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- H:
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Provides additional instructions and CSRs that control the new stage of
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address translation and support hosting a guest OS in virtual S-mode
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(VS-mode).
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- Zbb:
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RISC-V doesn't have a CLZ instruction in the base ISA.
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As a consequence, __builtin_ffs() emits a library call to ffs() on GCC,
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or a de Bruijn sequence on Clang.
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Zbb extension adds a CLZ instruction, after which __builtin_ffs() emits
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a very simple sequence.
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The similar issue occurs with other __builtin_<bitop>, so it is needed to
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provide a generic version of bitops in RISC-V bitops.h
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- Zihintpause:
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On a system that doesn't have this extension, cpu_relax() should be
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implemented properly.
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- SVPBMT is mandatory to enable changing the memory attributes of a page.
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For platforms that do not support SVPBMT, it is necessary to introduce a
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similar mechanism as described in:
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https://lore.kernel.org/all/20241102000843.1301099-1-samuel.holland@sifive.com/
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