mirror of
https://github.com/xen-project/xen.git
synced 2026-10-28 10:11:27 +01:00
Roger Pau Monné
e9b4fe2636
AMD Milan (Zen3) CPUs have an LFENCE Always Serialising CPUID bit in leaf 80000021.eax. Previous AMD versions used to have a user settable bit in DE_CFG MSR to select whether LFENCE was dispatch serialising, which Xen always attempts to set. The forcefully always on setting is due to the addition of SEV-SNP so that a VMM cannot break the confidentiality of a guest. In order to support this new CPUID bit move the LFENCE_DISPATCH synthetic CPUID bit to map the hardware bit (leaving a hole in the synthetic range) and either rely on the bit already being set by the native CPUID output, or attempt to fake it in Xen by modifying the DE_CFG MSR. This requires adding one more entry to the featureset to support leaf 80000021.eax. The bit is always exposed to guests by default even if the underlying hardware doesn't support leaf 80000021. Note that Xen doesn't allow guests to change the DE_CFG value, so once set by Xen LFENCE will always be serialising. Note that the access to DE_CFG by guests is left as-is: reads will unconditionally return LFENCE_SERIALISE bit set, while writes are silently dropped. Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com> Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com> [Always expose to guests by default] Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>