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Igor Druzhinin
b05ec9263e
Due to AMD and Hygon being unable to selectively trap CR4 bit modifications running 32-bit PV guest inside PV shim comes with significant performance hit. Moreover, for SMEP in particular every time CR4.SMEP changes on context switch to/from 32-bit PV guest, it gets trapped by L0 Xen which then tries to perform global TLB invalidation for PV shim domain. This usually results in eventual hang of a PV shim with at least several vCPUs. Since the overall security risk is generally lower for shim Xen as it being there more of a defense-in-depth mechanism, choose to disable SMEP/SMAP in it by default on AMD and Hygon unless a user chose otherwise. Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com> Reviewed-by: Jan Beulich <jbeulich@suse.com>
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