Bertrand Marquis fd7479b9ae xen/arm: Add workaround for Cortex-A55 erratum #1530923 ...

On the Cortex A55, TLB entries can be allocated by a speculative AT
instruction. If this is happening during a guest context switch with an
inconsistent page table state in the guest, TLBs with wrong values might
be allocated.
The ARM64_WORKAROUND_AT_SPECULATE workaround is used as for erratum
1165522 on Cortex A76 or Neoverse N1.

This change is also introducing the MIDR identifier for the Cortex-A55.

Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
Reviewed-by: Rahul Singh <rahul.singh@arm.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Acked-by: Julien Grall <jgrall@amazon.com>

2020-11-25 11:17:27 +00:00

..

device-tree

xen/docs: arm: Update dom0less binding and example

2019-10-10 15:50:00 +01:00

big.LITTLE.txt

xen/arm: update the docs about heterogeneous computing

2018-03-06 11:32:51 -08:00

booting.txt

misc/arm: Correctly name bit in the booting document

2016-09-21 11:23:32 -07:00

early-printk.txt

xen/arm: Configure early printk via Kconfig

2020-04-01 10:49:33 +01:00

passthrough.txt

xen/arm: add dom0-less device assignment info to docs

2019-10-04 10:16:58 -07:00

silicon-errata.txt

xen/arm: Add workaround for Cortex-A55 erratum #1530923

2020-11-25 11:17:27 +00:00