mirror of
https://github.com/xen-project/xen.git
synced 2026-10-29 10:40:03 +01:00
Ian Campbell
26f91ef506
Fixes ioemu stubdom build: CC i386-stubdom/piix4acpi.o [...]/stubdom/ioemu/hw/piix4acpi.c:272: error: expected ')' before '?' token [...]/stubdom/ioemu/hw/piix4acpi.c:277: error: conflicting types for 'set_bit' [...]/stubdom/../extras/mini-os/include/x86/mini-os/os.h:396: error: previous definition of 'set_bit' was here [...]/stubdom/ioemu/hw/piix4acpi.c:282: error: conflicting types for 'clear_bit' [...]/stubdom/../extras/mini-os/include/x86/mini-os/os.h:414: error: previous definition of 'clear_bit' was here [...]/stubdom/ioemu/hw/piix4acpi.c: In function 'gpe_sts_write': Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Ian Jackson <ian.jackson@eu.citrix.com> Committed-by: Ian Jackson <ian.jackson@eu.citrix.com>
573 lines
15 KiB
C
573 lines
15 KiB
C
/******************************************************************************
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* os.h
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*
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* random collection of macros and definition
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*/
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#ifndef _OS_H_
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#define _OS_H_
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#if __GNUC__ == 2 && __GNUC_MINOR__ < 96
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#define __builtin_expect(x, expected_value) (x)
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#endif
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#define unlikely(x) __builtin_expect((x),0)
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#define likely(x) __builtin_expect((x),1)
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#define smp_processor_id() 0
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#ifndef __ASSEMBLY__
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#include <mini-os/types.h>
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#include <mini-os/hypervisor.h>
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#include <mini-os/kernel.h>
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#define USED __attribute__ ((used))
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#define BUG do_exit
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#endif
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#include <xen/xen.h>
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#define __KERNEL_CS FLAT_KERNEL_CS
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#define __KERNEL_DS FLAT_KERNEL_DS
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#define __KERNEL_SS FLAT_KERNEL_SS
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#define TRAP_divide_error 0
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#define TRAP_debug 1
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#define TRAP_nmi 2
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#define TRAP_int3 3
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#define TRAP_overflow 4
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#define TRAP_bounds 5
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#define TRAP_invalid_op 6
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#define TRAP_no_device 7
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#define TRAP_double_fault 8
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#define TRAP_copro_seg 9
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#define TRAP_invalid_tss 10
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#define TRAP_no_segment 11
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#define TRAP_stack_error 12
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#define TRAP_gp_fault 13
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#define TRAP_page_fault 14
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#define TRAP_spurious_int 15
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#define TRAP_copro_error 16
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#define TRAP_alignment_check 17
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#define TRAP_machine_check 18
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#define TRAP_simd_error 19
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#define TRAP_deferred_nmi 31
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/* Everything below this point is not included by assembler (.S) files. */
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#ifndef __ASSEMBLY__
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extern shared_info_t *HYPERVISOR_shared_info;
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void trap_init(void);
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void trap_fini(void);
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void arch_init(start_info_t *si);
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void arch_print_info(void);
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void arch_fini(void);
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/*
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* The use of 'barrier' in the following reflects their use as local-lock
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* operations. Reentrancy must be prevented (e.g., __cli()) /before/ following
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* critical operations are executed. All critical operations must complete
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* /before/ reentrancy is permitted (e.g., __sti()). Alpha architecture also
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* includes these barriers, for example.
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*/
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#define __cli() \
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do { \
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vcpu_info_t *_vcpu; \
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_vcpu = &HYPERVISOR_shared_info->vcpu_info[smp_processor_id()]; \
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_vcpu->evtchn_upcall_mask = 1; \
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barrier(); \
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} while (0)
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#define __sti() \
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do { \
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vcpu_info_t *_vcpu; \
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barrier(); \
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_vcpu = &HYPERVISOR_shared_info->vcpu_info[smp_processor_id()]; \
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_vcpu->evtchn_upcall_mask = 0; \
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barrier(); /* unmask then check (avoid races) */ \
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if ( unlikely(_vcpu->evtchn_upcall_pending) ) \
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force_evtchn_callback(); \
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} while (0)
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#define __save_flags(x) \
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do { \
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vcpu_info_t *_vcpu; \
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_vcpu = &HYPERVISOR_shared_info->vcpu_info[smp_processor_id()]; \
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(x) = _vcpu->evtchn_upcall_mask; \
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} while (0)
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#define __restore_flags(x) \
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do { \
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vcpu_info_t *_vcpu; \
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barrier(); \
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_vcpu = &HYPERVISOR_shared_info->vcpu_info[smp_processor_id()]; \
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if ((_vcpu->evtchn_upcall_mask = (x)) == 0) { \
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barrier(); /* unmask then check (avoid races) */ \
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if ( unlikely(_vcpu->evtchn_upcall_pending) ) \
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force_evtchn_callback(); \
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}\
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} while (0)
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#define safe_halt() ((void)0)
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#define __save_and_cli(x) \
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do { \
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vcpu_info_t *_vcpu; \
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_vcpu = &HYPERVISOR_shared_info->vcpu_info[smp_processor_id()]; \
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(x) = _vcpu->evtchn_upcall_mask; \
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_vcpu->evtchn_upcall_mask = 1; \
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barrier(); \
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} while (0)
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#define local_irq_save(x) __save_and_cli(x)
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#define local_irq_restore(x) __restore_flags(x)
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#define local_save_flags(x) __save_flags(x)
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#define local_irq_disable() __cli()
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#define local_irq_enable() __sti()
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#define irqs_disabled() \
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HYPERVISOR_shared_info->vcpu_info[smp_processor_id()].evtchn_upcall_mask
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/* This is a barrier for the compiler only, NOT the processor! */
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#define barrier() __asm__ __volatile__("": : :"memory")
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#if defined(__i386__)
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#define mb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
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#define rmb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
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#define wmb() __asm__ __volatile__ ("": : :"memory")
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#elif defined(__x86_64__)
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#define mb() __asm__ __volatile__ ("mfence":::"memory")
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#define rmb() __asm__ __volatile__ ("lfence":::"memory")
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#define wmb() __asm__ __volatile__ ("sfence" ::: "memory") /* From CONFIG_UNORDERED_IO (linux) */
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#endif
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#define LOCK_PREFIX ""
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#define LOCK ""
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#define ADDR (*(volatile long *) addr)
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/*
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* Make sure gcc doesn't try to be clever and move things around
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* on us. We need to use _exactly_ the address the user gave us,
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* not some alias that contains the same information.
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*/
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typedef struct { volatile int counter; } atomic_t;
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/************************** i386 *******************************/
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#ifdef __INSIDE_MINIOS__
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#if defined (__i386__)
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#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((struct __xchg_dummy *)(x))
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__("xchgb %b0,%1"
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:"=q" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 2:
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__asm__ __volatile__("xchgw %w0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 4:
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__asm__ __volatile__("xchgl %0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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}
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return x;
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}
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/**
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It can be reorderdered on other architectures other than x86.
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* It also implies a memory barrier.
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*/
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static inline int test_and_clear_bit(int nr, volatile unsigned long * addr)
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{
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int oldbit;
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__asm__ __volatile__( LOCK
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"btrl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),"=m" (ADDR)
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:"Ir" (nr) : "memory");
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return oldbit;
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}
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static inline int constant_test_bit(int nr, const volatile unsigned long *addr)
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{
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return ((1UL << (nr & 31)) & (addr[nr >> 5])) != 0;
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}
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static inline int variable_test_bit(int nr, const volatile unsigned long * addr)
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{
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int oldbit;
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__asm__ __volatile__(
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"btl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit)
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:"m" (ADDR),"Ir" (nr));
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return oldbit;
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}
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#define test_bit(nr,addr) \
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(__builtin_constant_p(nr) ? \
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constant_test_bit((nr),(addr)) : \
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variable_test_bit((nr),(addr)))
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/**
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered. See __set_bit()
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* if you do not require the atomic guarantees.
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*
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* Note: there are no guarantees that this function will not be reordered
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* on non x86 architectures, so if you are writting portable code,
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* make sure not to rely on its reordering guarantees.
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*
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void set_bit(int nr, volatile unsigned long * addr)
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{
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__asm__ __volatile__( LOCK
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"btsl %1,%0"
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:"=m" (ADDR)
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:"Ir" (nr));
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}
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/**
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* clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit() is atomic and may not be reordered. However, it does
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* not contain a memory barrier, so if it is used for locking purposes,
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
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* in order to ensure changes are visible on other processors.
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*/
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static inline void clear_bit(int nr, volatile unsigned long * addr)
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{
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__asm__ __volatile__( LOCK
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"btrl %1,%0"
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:"=m" (ADDR)
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:"Ir" (nr));
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}
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/**
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* __ffs - find first bit in word.
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* @word: The word to search
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*
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* Undefined if no bit exists, so code should check against 0 first.
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*/
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static inline unsigned long __ffs(unsigned long word)
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{
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__asm__("bsfl %1,%0"
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:"=r" (word)
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:"rm" (word));
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return word;
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}
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/*
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* These have to be done with inline assembly: that way the bit-setting
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* is guaranteed to be atomic. All bit operations return 0 if the bit
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* was cleared before the operation and != 0 if it was not.
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*
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* bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
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*/
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#define ADDR (*(volatile long *) addr)
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#define rdtscll(val) \
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__asm__ __volatile__("rdtsc" : "=A" (val))
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#elif defined(__x86_64__)/* ifdef __i386__ */
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/************************** x86_84 *******************************/
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#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
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#define __xg(x) ((volatile long *)(x))
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__("xchgb %b0,%1"
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:"=q" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 2:
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__asm__ __volatile__("xchgw %w0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 4:
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__asm__ __volatile__("xchgl %k0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 8:
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__asm__ __volatile__("xchgq %0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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}
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return x;
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}
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/**
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
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{
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int oldbit;
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__asm__ __volatile__( LOCK_PREFIX
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"btrl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),"=m" (ADDR)
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:"dIr" (nr) : "memory");
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return oldbit;
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}
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static __inline__ int constant_test_bit(int nr, const volatile void * addr)
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{
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return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
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}
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static __inline__ int variable_test_bit(int nr, volatile const void * addr)
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{
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int oldbit;
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__asm__ __volatile__(
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"btl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit)
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:"m" (ADDR),"dIr" (nr));
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return oldbit;
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}
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#define test_bit(nr,addr) \
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(__builtin_constant_p(nr) ? \
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constant_test_bit((nr),(addr)) : \
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variable_test_bit((nr),(addr)))
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/**
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered. See __set_bit()
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* if you do not require the atomic guarantees.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static __inline__ void set_bit(int nr, volatile void * addr)
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{
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__asm__ __volatile__( LOCK_PREFIX
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"btsl %1,%0"
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:"=m" (ADDR)
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:"dIr" (nr) : "memory");
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}
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/**
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* clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit() is atomic and may not be reordered. However, it does
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* not contain a memory barrier, so if it is used for locking purposes,
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
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* in order to ensure changes are visible on other processors.
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*/
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static __inline__ void clear_bit(int nr, volatile void * addr)
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{
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__asm__ __volatile__( LOCK_PREFIX
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"btrl %1,%0"
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:"=m" (ADDR)
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:"dIr" (nr));
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}
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/**
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* __ffs - find first bit in word.
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* @word: The word to search
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*
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* Undefined if no bit exists, so code should check against 0 first.
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*/
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static __inline__ unsigned long __ffs(unsigned long word)
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{
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__asm__("bsfq %1,%0"
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:"=r" (word)
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:"rm" (word));
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return word;
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}
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#define ADDR (*(volatile long *) addr)
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#define rdtscll(val) do { \
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unsigned int __a,__d; \
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asm volatile("rdtsc" : "=a" (__a), "=d" (__d)); \
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(val) = ((unsigned long)__a) | (((unsigned long)__d)<<32); \
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} while(0)
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#define wrmsr(msr,val1,val2) \
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__asm__ __volatile__("wrmsr" \
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: /* no outputs */ \
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: "c" (msr), "a" (val1), "d" (val2))
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#define wrmsrl(msr,val) wrmsr(msr,(uint32_t)((uint64_t)(val)),((uint64_t)(val))>>32)
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#else /* ifdef __x86_64__ */
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#error "Unsupported architecture"
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#endif
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#endif /* ifdef __INSIDE_MINIOS */
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/********************* common i386 and x86_64 ****************************/
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struct __synch_xchg_dummy { unsigned long a[100]; };
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#define __synch_xg(x) ((struct __synch_xchg_dummy *)(x))
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#define synch_cmpxchg(ptr, old, new) \
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((__typeof__(*(ptr)))__synch_cmpxchg((ptr),\
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(unsigned long)(old), \
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(unsigned long)(new), \
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sizeof(*(ptr))))
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static inline unsigned long __synch_cmpxchg(volatile void *ptr,
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unsigned long old,
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unsigned long new, int size)
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{
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unsigned long prev;
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switch (size) {
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case 1:
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__asm__ __volatile__("lock; cmpxchgb %b1,%2"
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: "=a"(prev)
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: "q"(new), "m"(*__synch_xg(ptr)),
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"0"(old)
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: "memory");
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return prev;
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case 2:
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__asm__ __volatile__("lock; cmpxchgw %w1,%2"
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: "=a"(prev)
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: "r"(new), "m"(*__synch_xg(ptr)),
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"0"(old)
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: "memory");
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return prev;
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#ifdef __x86_64__
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case 4:
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__asm__ __volatile__("lock; cmpxchgl %k1,%2"
|
|
: "=a"(prev)
|
|
: "r"(new), "m"(*__synch_xg(ptr)),
|
|
"0"(old)
|
|
: "memory");
|
|
return prev;
|
|
case 8:
|
|
__asm__ __volatile__("lock; cmpxchgq %1,%2"
|
|
: "=a"(prev)
|
|
: "r"(new), "m"(*__synch_xg(ptr)),
|
|
"0"(old)
|
|
: "memory");
|
|
return prev;
|
|
#else
|
|
case 4:
|
|
__asm__ __volatile__("lock; cmpxchgl %1,%2"
|
|
: "=a"(prev)
|
|
: "r"(new), "m"(*__synch_xg(ptr)),
|
|
"0"(old)
|
|
: "memory");
|
|
return prev;
|
|
#endif
|
|
}
|
|
return old;
|
|
}
|
|
|
|
|
|
static __inline__ void synch_set_bit(int nr, volatile void * addr)
|
|
{
|
|
__asm__ __volatile__ (
|
|
"lock btsl %1,%0"
|
|
: "=m" (ADDR) : "Ir" (nr) : "memory" );
|
|
}
|
|
|
|
static __inline__ void synch_clear_bit(int nr, volatile void * addr)
|
|
{
|
|
__asm__ __volatile__ (
|
|
"lock btrl %1,%0"
|
|
: "=m" (ADDR) : "Ir" (nr) : "memory" );
|
|
}
|
|
|
|
static __inline__ int synch_test_and_set_bit(int nr, volatile void * addr)
|
|
{
|
|
int oldbit;
|
|
__asm__ __volatile__ (
|
|
"lock btsl %2,%1\n\tsbbl %0,%0"
|
|
: "=r" (oldbit), "=m" (ADDR) : "Ir" (nr) : "memory");
|
|
return oldbit;
|
|
}
|
|
|
|
static __inline__ int synch_test_and_clear_bit(int nr, volatile void * addr)
|
|
{
|
|
int oldbit;
|
|
__asm__ __volatile__ (
|
|
"lock btrl %2,%1\n\tsbbl %0,%0"
|
|
: "=r" (oldbit), "=m" (ADDR) : "Ir" (nr) : "memory");
|
|
return oldbit;
|
|
}
|
|
|
|
static __inline__ int synch_const_test_bit(int nr, const volatile void * addr)
|
|
{
|
|
return ((1UL << (nr & 31)) &
|
|
(((const volatile unsigned int *) addr)[nr >> 5])) != 0;
|
|
}
|
|
|
|
static __inline__ int synch_var_test_bit(int nr, volatile void * addr)
|
|
{
|
|
int oldbit;
|
|
__asm__ __volatile__ (
|
|
"btl %2,%1\n\tsbbl %0,%0"
|
|
: "=r" (oldbit) : "m" (ADDR), "Ir" (nr) );
|
|
return oldbit;
|
|
}
|
|
|
|
#define synch_test_bit(nr,addr) \
|
|
(__builtin_constant_p(nr) ? \
|
|
synch_const_test_bit((nr),(addr)) : \
|
|
synch_var_test_bit((nr),(addr)))
|
|
|
|
|
|
#undef ADDR
|
|
|
|
#endif /* not assembly */
|
|
#endif /* _OS_H_ */
|