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https://github.com/xen-project/xen.git
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Jean Guyader
cefeffc7e5
The Intel GPU uses a two pages NVS region called OpRegion. In order to get full support for the driver in the guest we need to map this region. This patch reserves 2 pages on the top of the memory in the reserved area and mark this region as NVS in the e820. Then we write the address to the config space (offset 0xfc) so the device model can map the OpRegion at this address in the guest. Signed-off-by: Jean Guyader <jean.guyader@eu.citrix.com> Committed-by: Keir Fraser <keir@xen.org>
297 lines
10 KiB
C
297 lines
10 KiB
C
/*
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* pci.c: HVM PCI setup.
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*
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* Leendert van Doorn, leendert@watson.ibm.com
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* Copyright (c) 2005, International Business Machines Corporation.
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*
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* Copyright (c) 2006, Keir Fraser, XenSource Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*/
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#include "util.h"
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#include "hypercall.h"
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#include "config.h"
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#include "pci_regs.h"
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#include <xen/memory.h>
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#include <xen/hvm/ioreq.h>
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unsigned long pci_mem_start = PCI_MEM_START;
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unsigned long pci_mem_end = PCI_MEM_END;
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enum virtual_vga virtual_vga = VGA_none;
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unsigned long igd_opregion_pgbase = 0;
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void pci_setup(void)
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{
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uint32_t base, devfn, bar_reg, bar_data, bar_sz, cmd, mmio_total = 0;
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uint32_t vga_devfn = 256;
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uint16_t class, vendor_id, device_id;
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unsigned int bar, pin, link, isa_irq;
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/* Resources assignable to PCI devices via BARs. */
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struct resource {
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uint32_t base, max;
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} *resource, mem_resource, io_resource;
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/* Create a list of device BARs in descending order of size. */
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struct bars {
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uint32_t devfn, bar_reg, bar_sz;
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} *bars = (struct bars *)scratch_start;
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unsigned int i, nr_bars = 0;
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/* Program PCI-ISA bridge with appropriate link routes. */
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isa_irq = 0;
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for ( link = 0; link < 4; link++ )
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{
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do { isa_irq = (isa_irq + 1) & 15;
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} while ( !(PCI_ISA_IRQ_MASK & (1U << isa_irq)) );
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pci_writeb(PCI_ISA_DEVFN, 0x60 + link, isa_irq);
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printf("PCI-ISA link %u routed to IRQ%u\n", link, isa_irq);
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}
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/* Program ELCR to match PCI-wired IRQs. */
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outb(0x4d0, (uint8_t)(PCI_ISA_IRQ_MASK >> 0));
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outb(0x4d1, (uint8_t)(PCI_ISA_IRQ_MASK >> 8));
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/* Scan the PCI bus and map resources. */
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for ( devfn = 0; devfn < 256; devfn++ )
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{
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class = pci_readw(devfn, PCI_CLASS_DEVICE);
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vendor_id = pci_readw(devfn, PCI_VENDOR_ID);
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device_id = pci_readw(devfn, PCI_DEVICE_ID);
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if ( (vendor_id == 0xffff) && (device_id == 0xffff) )
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continue;
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ASSERT((devfn != PCI_ISA_DEVFN) ||
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((vendor_id == 0x8086) && (device_id == 0x7000)));
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switch ( class )
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{
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case 0x0300:
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/* If emulated VGA is found, preserve it as primary VGA. */
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if ( (vendor_id == 0x1234) && (device_id == 0x1111) )
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{
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vga_devfn = devfn;
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virtual_vga = VGA_std;
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}
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else if ( (vendor_id == 0x1013) && (device_id == 0xb8) )
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{
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vga_devfn = devfn;
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virtual_vga = VGA_cirrus;
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}
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else if ( virtual_vga == VGA_none )
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{
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vga_devfn = devfn;
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virtual_vga = VGA_pt;
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if ( vendor_id == 0x8086 )
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{
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igd_opregion_pgbase = mem_hole_alloc(2);
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/*
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* Write the the OpRegion offset to give the opregion
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* address to the device model. The device model will trap
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* and map the OpRegion at the give address.
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*/
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pci_writel(vga_devfn, PCI_INTEL_OPREGION,
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igd_opregion_pgbase << PAGE_SHIFT);
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}
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}
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break;
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case 0x0680:
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/* PIIX4 ACPI PM. Special device with special PCI config space. */
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ASSERT((vendor_id == 0x8086) && (device_id == 0x7113));
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pci_writew(devfn, 0x20, 0x0000); /* No smb bus IO enable */
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pci_writew(devfn, 0xd2, 0x0000); /* No smb bus IO enable */
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pci_writew(devfn, 0x22, 0x0000);
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pci_writew(devfn, 0x3c, 0x0009); /* Hardcoded IRQ9 */
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pci_writew(devfn, 0x3d, 0x0001);
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pci_writel(devfn, 0x40, ACPI_PM1A_EVT_BLK_ADDRESS_V1 | 1);
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pci_writeb(devfn, 0x80, 0x01); /* enable PM io space */
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break;
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case 0x0101:
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if ( vendor_id == 0x8086 )
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{
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/* Intel ICHs since PIIX3: enable IDE legacy mode. */
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pci_writew(devfn, 0x40, 0x8000); /* enable IDE0 */
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pci_writew(devfn, 0x42, 0x8000); /* enable IDE1 */
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}
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break;
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}
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/* Map the I/O memory and port resources. */
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for ( bar = 0; bar < 7; bar++ )
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{
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bar_reg = PCI_BASE_ADDRESS_0 + 4*bar;
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if ( bar == 6 )
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bar_reg = PCI_ROM_ADDRESS;
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bar_data = pci_readl(devfn, bar_reg);
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pci_writel(devfn, bar_reg, ~0);
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bar_sz = pci_readl(devfn, bar_reg);
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pci_writel(devfn, bar_reg, bar_data);
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if ( bar_sz == 0 )
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continue;
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bar_sz &= (((bar_data & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_MEMORY) ?
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PCI_BASE_ADDRESS_MEM_MASK :
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(PCI_BASE_ADDRESS_IO_MASK & 0xffff));
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bar_sz &= ~(bar_sz - 1);
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for ( i = 0; i < nr_bars; i++ )
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if ( bars[i].bar_sz < bar_sz )
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break;
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if ( i != nr_bars )
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memmove(&bars[i+1], &bars[i], (nr_bars-i) * sizeof(*bars));
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bars[i].devfn = devfn;
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bars[i].bar_reg = bar_reg;
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bars[i].bar_sz = bar_sz;
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if ( (bar_data & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_MEMORY )
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mmio_total += bar_sz;
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nr_bars++;
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/* Skip the upper-half of the address for a 64-bit BAR. */
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if ( (bar_data & (PCI_BASE_ADDRESS_SPACE |
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PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
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(PCI_BASE_ADDRESS_SPACE_MEMORY |
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PCI_BASE_ADDRESS_MEM_TYPE_64) )
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bar++;
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}
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/* Map the interrupt. */
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pin = pci_readb(devfn, PCI_INTERRUPT_PIN);
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if ( pin != 0 )
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{
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/* This is the barber's pole mapping used by Xen. */
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link = ((pin - 1) + (devfn >> 3)) & 3;
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isa_irq = pci_readb(PCI_ISA_DEVFN, 0x60 + link);
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pci_writeb(devfn, PCI_INTERRUPT_LINE, isa_irq);
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printf("pci dev %02x:%x INT%c->IRQ%u\n",
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devfn>>3, devfn&7, 'A'+pin-1, isa_irq);
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}
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/* Enable bus mastering. */
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cmd = pci_readw(devfn, PCI_COMMAND);
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cmd |= PCI_COMMAND_MASTER;
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pci_writew(devfn, PCI_COMMAND, cmd);
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}
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while ( (mmio_total > (pci_mem_end - pci_mem_start)) &&
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((pci_mem_start << 1) != 0) )
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pci_mem_start <<= 1;
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/* Relocate RAM that overlaps PCI space (in 64k-page chunks). */
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while ( (pci_mem_start >> PAGE_SHIFT) < hvm_info->low_mem_pgend )
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{
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struct xen_add_to_physmap xatp;
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unsigned int nr_pages = min_t(
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unsigned int,
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hvm_info->low_mem_pgend - (pci_mem_start >> PAGE_SHIFT),
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(1u << 16) - 1);
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if ( hvm_info->high_mem_pgend == 0 )
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hvm_info->high_mem_pgend = 1ull << (32 - PAGE_SHIFT);
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hvm_info->low_mem_pgend -= nr_pages;
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xatp.domid = DOMID_SELF;
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xatp.space = XENMAPSPACE_gmfn_range;
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xatp.idx = hvm_info->low_mem_pgend;
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xatp.gpfn = hvm_info->high_mem_pgend;
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xatp.size = nr_pages;
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if ( hypercall_memory_op(XENMEM_add_to_physmap, &xatp) != 0 )
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BUG();
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hvm_info->high_mem_pgend += nr_pages;
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}
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mem_resource.base = pci_mem_start;
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mem_resource.max = pci_mem_end;
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io_resource.base = 0xc000;
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io_resource.max = 0x10000;
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/* Assign iomem and ioport resources in descending order of size. */
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for ( i = 0; i < nr_bars; i++ )
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{
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devfn = bars[i].devfn;
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bar_reg = bars[i].bar_reg;
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bar_sz = bars[i].bar_sz;
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bar_data = pci_readl(devfn, bar_reg);
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if ( (bar_data & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_MEMORY )
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{
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resource = &mem_resource;
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bar_data &= ~PCI_BASE_ADDRESS_MEM_MASK;
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}
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else
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{
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resource = &io_resource;
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bar_data &= ~PCI_BASE_ADDRESS_IO_MASK;
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}
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base = (resource->base + bar_sz - 1) & ~(bar_sz - 1);
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bar_data |= base;
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base += bar_sz;
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if ( (base < resource->base) || (base > resource->max) )
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{
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printf("pci dev %02x:%x bar %02x size %08x: no space for "
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"resource!\n", devfn>>3, devfn&7, bar_reg, bar_sz);
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continue;
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}
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resource->base = base;
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pci_writel(devfn, bar_reg, bar_data);
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printf("pci dev %02x:%x bar %02x size %08x: %08x\n",
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devfn>>3, devfn&7, bar_reg, bar_sz, bar_data);
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/* Now enable the memory or I/O mapping. */
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cmd = pci_readw(devfn, PCI_COMMAND);
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if ( (bar_reg == PCI_ROM_ADDRESS) ||
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((bar_data & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_MEMORY) )
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cmd |= PCI_COMMAND_MEMORY;
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else
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cmd |= PCI_COMMAND_IO;
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pci_writew(devfn, PCI_COMMAND, cmd);
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}
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if ( vga_devfn != 256 )
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{
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/*
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* VGA registers live in I/O space so ensure that primary VGA
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* has IO enabled, even if there is no I/O BAR on that
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* particular device.
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*/
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cmd = pci_readw(vga_devfn, PCI_COMMAND);
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cmd |= PCI_COMMAND_IO;
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pci_writew(vga_devfn, PCI_COMMAND, cmd);
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}
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}
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/*
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* Local variables:
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* mode: C
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* c-set-style: "BSD"
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* c-basic-offset: 4
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* tab-width: 4
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* indent-tabs-mode: nil
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* End:
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*/
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