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https://github.com/xen-project/xen.git
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Jan Beulich
cef805dce4
Since the insns here and in particular their memory access patterns follow the usual scheme, I didn't think it was necessary to add a contrived test specifically for them. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
223 lines
7.2 KiB
C
223 lines
7.2 KiB
C
#ifndef X86_EMULATE_H
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#define X86_EMULATE_H
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#include <assert.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <stdlib.h>
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/*
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* Use of sse registers must be disabled prior to the definition of
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* always_inline functions that would use them (memcpy, memset, etc),
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* so do this as early as possible, aiming to be before any always_inline
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* functions that are used are declared.
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* Unfortunately, this cannot be done prior to inclusion of <stdlib.h>
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* due to functions such as 'atof' that have SSE register return declared,
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* so do so here, immediately after that.
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*/
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#if __GNUC__ >= 6
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# pragma GCC target("no-sse")
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#endif
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/*
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* Attempt detection of unwanted prior inclusion of some headers known to use
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* always_inline with SSE registers in some library / compiler / optimization
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* combinations.
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*/
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#ifdef _STRING_H
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# error "Must not include <string.h> before x86-emulate.h"
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#endif
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#include <string.h>
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/* EOF is a standard macro defined in <stdio.h> so use it for detection */
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#ifdef EOF
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# error "Must not include <stdio.h> before x86-emulate.h"
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#endif
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#include <stdio.h>
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#include <xen/xen.h>
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#include <xen/asm/msr-index.h>
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#include <xen/asm/x86-defns.h>
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#include <xen/asm/x86-vendors.h>
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#include <xen-tools/common-macros.h>
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#define BUG() abort()
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#define ASSERT assert
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#define ASSERT_UNREACHABLE() assert(!__LINE__)
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#define DEFINE_PER_CPU(type, var) type per_cpu_##var
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#define this_cpu(var) per_cpu_##var
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#define __init
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#define __maybe_unused __attribute__((__unused__))
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#define likely(x) __builtin_expect(!!(x), true)
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#define unlikely(x) __builtin_expect(!!(x), false)
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#define cf_check /* No Control Flow Integriy checking */
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#ifdef __GCC_ASM_FLAG_OUTPUTS__
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# define ASM_FLAG_OUT(yes, no) yes
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#else
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# define ASM_FLAG_OUT(yes, no) no
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#endif
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#define hweight32 __builtin_popcount
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#define hweight64 __builtin_popcountll
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#define is_canonical_address(x) (((int64_t)(x) >> 47) == ((int64_t)(x) >> 63))
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extern uint32_t mxcsr_mask;
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extern struct cpu_policy cp;
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#define MMAP_SZ 16384
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bool emul_test_init(void);
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/* Must save and restore FPU state between any call into libc. */
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void emul_save_fpu_state(void);
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void emul_restore_fpu_state(void);
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struct x86_fxsr *get_fpu_save_area(void);
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/*
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* In order to reasonably use the above, wrap library calls we use and which we
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* think might access any of the FPU state into wrappers saving/restoring state
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* around the actual function.
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*/
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#ifndef WRAP
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# define WRAP(x) typeof(x) __wrap_ ## x
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#endif
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WRAP(fwrite);
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WRAP(memcmp);
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WRAP(memcpy);
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WRAP(memset);
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WRAP(printf);
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WRAP(putchar);
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WRAP(puts);
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WRAP(snprintf);
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WRAP(strstr);
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WRAP(vprintf);
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WRAP(vsnprintf);
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#undef WRAP
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#include "x86_emulate/x86_emulate.h"
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void evex_disp8_test(void *instr, struct x86_emulate_ctxt *ctxt,
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const struct x86_emulate_ops *ops);
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void predicates_test(void *instr, struct x86_emulate_ctxt *ctxt,
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int (*fetch)(unsigned long offset,
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void *p_data,
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unsigned int bytes,
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struct x86_emulate_ctxt *ctxt));
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static inline uint64_t xgetbv(uint32_t xcr)
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{
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uint32_t lo, hi;
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asm ( ".byte 0x0f, 0x01, 0xd0" : "=a" (lo), "=d" (hi) : "c" (xcr) );
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return ((uint64_t)hi << 32) | lo;
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}
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/* Intentionally checking OSXSAVE here. */
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#define cpu_has_xsave (cp.basic.raw[1].c & (1u << 27))
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static inline bool xcr0_mask(uint64_t mask)
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{
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return cpu_has_xsave && ((xgetbv(0) & mask) == mask);
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}
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unsigned int rdpkru(void);
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void wrpkru(unsigned int val);
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#define cache_line_size() (cp.basic.clflush_size * 8)
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#define cpu_has_fpu cp.basic.fpu
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#define cpu_has_mmx cp.basic.mmx
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#define cpu_has_fxsr cp.basic.fxsr
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#define cpu_has_sse cp.basic.sse
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#define cpu_has_sse2 cp.basic.sse2
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#define cpu_has_sse3 cp.basic.sse3
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#define cpu_has_pclmulqdq cp.basic.pclmulqdq
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#define cpu_has_ssse3 cp.basic.ssse3
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#define cpu_has_fma (cp.basic.fma && xcr0_mask(6))
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#define cpu_has_sse4_1 cp.basic.sse4_1
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#define cpu_has_sse4_2 cp.basic.sse4_2
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#define cpu_has_popcnt cp.basic.popcnt
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#define cpu_has_aesni cp.basic.aesni
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#define cpu_has_avx (cp.basic.avx && xcr0_mask(6))
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#define cpu_has_f16c (cp.basic.f16c && xcr0_mask(6))
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#define cpu_has_avx2 (cp.feat.avx2 && xcr0_mask(6))
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#define cpu_has_bmi1 cp.feat.bmi1
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#define cpu_has_bmi2 cp.feat.bmi2
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#define cpu_has_avx512f (cp.feat.avx512f && xcr0_mask(0xe6))
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#define cpu_has_avx512dq (cp.feat.avx512dq && xcr0_mask(0xe6))
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#define cpu_has_avx512_ifma (cp.feat.avx512_ifma && xcr0_mask(0xe6))
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#define cpu_has_avx512er (cp.feat.avx512er && xcr0_mask(0xe6))
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#define cpu_has_avx512cd (cp.feat.avx512cd && xcr0_mask(0xe6))
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#define cpu_has_sha cp.feat.sha
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#define cpu_has_avx512bw (cp.feat.avx512bw && xcr0_mask(0xe6))
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#define cpu_has_avx512vl (cp.feat.avx512vl && xcr0_mask(0xe6))
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#define cpu_has_avx512_vbmi (cp.feat.avx512_vbmi && xcr0_mask(0xe6))
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#define cpu_has_avx512_vbmi2 (cp.feat.avx512_vbmi2 && xcr0_mask(0xe6))
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#define cpu_has_gfni cp.feat.gfni
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#define cpu_has_vaes (cp.feat.vaes && xcr0_mask(6))
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#define cpu_has_vpclmulqdq (cp.feat.vpclmulqdq && xcr0_mask(6))
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#define cpu_has_avx512_vnni (cp.feat.avx512_vnni && xcr0_mask(0xe6))
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#define cpu_has_avx512_bitalg (cp.feat.avx512_bitalg && xcr0_mask(0xe6))
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#define cpu_has_avx512_vpopcntdq (cp.feat.avx512_vpopcntdq && xcr0_mask(0xe6))
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#define cpu_has_movdiri cp.feat.movdiri
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#define cpu_has_movdir64b cp.feat.movdir64b
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#define cpu_has_avx512_4vnniw (cp.feat.avx512_4vnniw && xcr0_mask(0xe6))
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#define cpu_has_avx512_4fmaps (cp.feat.avx512_4fmaps && xcr0_mask(0xe6))
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#define cpu_has_avx512_vp2intersect (cp.feat.avx512_vp2intersect && xcr0_mask(0xe6))
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#define cpu_has_serialize cp.feat.serialize
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#define cpu_has_avx512_fp16 (cp.feat.avx512_fp16 && xcr0_mask(0xe6))
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#define cpu_has_sha512 (cp.feat.sha512 && xcr0_mask(6))
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#define cpu_has_sm3 (cp.feat.sm3 && xcr0_mask(6))
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#define cpu_has_sm4 (cp.feat.sm4 && xcr0_mask(6))
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#define cpu_has_avx_vnni (cp.feat.avx_vnni && xcr0_mask(6))
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#define cpu_has_avx512_bf16 (cp.feat.avx512_bf16 && xcr0_mask(0xe6))
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#define cpu_has_avx_ifma (cp.feat.avx_ifma && xcr0_mask(6))
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#define cpu_has_avx_vnni_int8 (cp.feat.avx_vnni_int8 && xcr0_mask(6))
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#define cpu_has_avx_ne_convert (cp.feat.avx_ne_convert && xcr0_mask(6))
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#define cpu_has_avx_vnni_int16 (cp.feat.avx_vnni_int16 && xcr0_mask(6))
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#define cpu_has_xgetbv1 (cpu_has_xsave && cp.xstate.xgetbv1)
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#define cpu_has_3dnow_ext cp.extd._3dnowext
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#define cpu_has_sse4a cp.extd.sse4a
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#define cpu_has_xop (cp.extd.xop && xcr0_mask(6))
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#define cpu_has_fma4 (cp.extd.fma4 && xcr0_mask(6))
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#define cpu_has_tbm cp.extd.tbm
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int emul_test_cpuid(
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uint32_t leaf,
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uint32_t subleaf,
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struct cpuid_leaf *res,
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struct x86_emulate_ctxt *ctxt);
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int emul_test_read_cr(
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unsigned int reg,
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unsigned long *val,
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struct x86_emulate_ctxt *ctxt);
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int emul_test_read_xcr(
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unsigned int reg,
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uint64_t *val,
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struct x86_emulate_ctxt *ctxt);
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int emul_test_get_fpu(
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enum x86_emulate_fpu_type type,
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struct x86_emulate_ctxt *ctxt);
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void emul_test_put_fpu(
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struct x86_emulate_ctxt *ctxt,
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enum x86_emulate_fpu_type backout,
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const struct x86_emul_fpu_aux *aux);
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#endif /* X86_EMULATE_H */
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