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arun.sharma@intel.com[kaf24]
a920220cef
[PATCH] ACPI support for guest firmware. ACPI support for guest firmware. Signed-off-by: Ke Yu <ke.yu@intel.com> Signed-off-by: Arun Sharma <arun.sharma@intel.com>
166 lines
5.0 KiB
C
166 lines
5.0 KiB
C
/*
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* Copyright (c) 2004, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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*/
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#ifndef _FADT_H_
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#define _FADT_H_
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//
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// FADT Definitions, see ACPI 2.0 specification for details.
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//
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#define ACPI_OEM_FADT_REVISION 0x00000000 // TBD
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#define ACPI_PREFERRED_PM_PROFILE 0x04
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#define ACPI_SCI_INT 0x0009
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#define ACPI_SMI_CMD 0x000000B2
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#define ACPI_ACPI_ENABLE 0x00
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#define ACPI_ACPI_DISABLE 0x00
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#define ACPI_S4_BIOS_REQ 0x00
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#define ACPI_PSTATE_CNT 0x00
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#define ACPI_GPE1_BASE 0x20
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#define ACPI_CST_CNT 0x00
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#define ACPI_P_LVL2_LAT 0x0065
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#define ACPI_P_LVL3_LAT 0X03E9
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#define ACPI_FLUSH_SIZE 0x00
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#define ACPI_FLUSH_STRIDE 0x00
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#define ACPI_DUTY_OFFSET 0x01
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#define ACPI_DUTY_WIDTH 0x00
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#define ACPI_DAY_ALRM 0x00
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#define ACPI_MON_ALRM 0x00
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#define ACPI_CENTURY 0x00
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//
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// IA-PC Boot Architecture Flags, see ACPI 2.0 table specification and Acpi2_0.h
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//
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#define ACPI_IAPC_BOOT_ARCH (ACPI_LEGACY_DEVICES | ACPI_8042)
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//
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// Fixed Feature Flags
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//
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#define ACPI_FIXED_FEATURE_FLAGS (ACPI_SLP_BUTTON| ACPI_WBINVD )
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//
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// PM1A Event Register Block Generic Address Information
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//
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#define ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID ACPI_SYSTEM_IO
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#define ACPI_PM1A_EVT_BLK_BIT_WIDTH 0x00
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#define ACPI_PM1A_EVT_BLK_BIT_OFFSET 0x00
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#define ACPI_PM1A_EVT_BLK_ADDRESS 0x0000000000000000
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//
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// PM1B Event Register Block Generic Address Information
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//
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#define ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID ACPI_SYSTEM_IO
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#define ACPI_PM1B_EVT_BLK_BIT_WIDTH 0x00
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#define ACPI_PM1B_EVT_BLK_BIT_OFFSET 0x00
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#define ACPI_PM1B_EVT_BLK_ADDRESS 0x0000000000000000
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//
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// PM1A Control Register Block Generic Address Information
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//
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#define ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID ACPI_SYSTEM_IO
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#define ACPI_PM1A_CNT_BLK_BIT_WIDTH 0x10
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#define ACPI_PM1A_CNT_BLK_BIT_OFFSET 0x00
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#define ACPI_PM1A_CNT_BLK_ADDRESS (ACPI_PM1A_EVT_BLK_ADDRESS + 0x04)
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//
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// PM1B Control Register Block Generic Address Information
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//
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#define ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID ACPI_SYSTEM_IO
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#define ACPI_PM1B_CNT_BLK_BIT_WIDTH 0x00
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#define ACPI_PM1B_CNT_BLK_BIT_OFFSET 0x00
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#define ACPI_PM1B_CNT_BLK_ADDRESS 0x0000000000000000
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//
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// PM2 Control Register Block Generic Address Information
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//
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#define ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID ACPI_SYSTEM_IO
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#define ACPI_PM2_CNT_BLK_BIT_WIDTH 0x00
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#define ACPI_PM2_CNT_BLK_BIT_OFFSET 0x00
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#define ACPI_PM2_CNT_BLK_ADDRESS 0x0000000000000000
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//
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// Power Management Timer Control Register Block Generic Address
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// Information
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//
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#define ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID ACPI_SYSTEM_IO
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#define ACPI_PM_TMR_BLK_BIT_WIDTH 0x20
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#define ACPI_PM_TMR_BLK_BIT_OFFSET 0x00
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#define ACPI_PM_TMR_BLK_ADDRESS (ACPI_PM1A_EVT_BLK_ADDRESS + 0x08)
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//
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// General Purpose Event 0 Register Block Generic Address
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// Information
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//
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#define ACPI_GPE0_BLK_ADDRESS_SPACE_ID ACPI_SYSTEM_IO
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#define ACPI_GPE0_BLK_BIT_WIDTH 0x00
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#define ACPI_GPE0_BLK_BIT_OFFSET 0x00
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#define ACPI_GPE0_BLK_ADDRESS 0x00
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//
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// General Purpose Event 1 Register Block Generic Address
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// Information
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//
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#define ACPI_GPE1_BLK_ADDRESS_SPACE_ID ACPI_SYSTEM_IO
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#define ACPI_GPE1_BLK_BIT_WIDTH 0x00
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#define ACPI_GPE1_BLK_BIT_OFFSET 0x00
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#define ACPI_GPE1_BLK_ADDRESS 0x00
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//
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// Reset Register Generic Address Information
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//
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#define ACPI_RESET_REG_ADDRESS_SPACE_ID ACPI_SYSTEM_IO
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#define ACPI_RESET_REG_BIT_WIDTH 0x08
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#define ACPI_RESET_REG_BIT_OFFSET 0x00
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#define ACPI_RESET_REG_ADDRESS 0x0000000000000CF9
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#define ACPI_RESET_VALUE 0x06
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//
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// Number of bytes decoded by PM1 event blocks (a and b)
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//
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#define ACPI_PM1_EVT_LEN ((ACPI_PM1A_EVT_BLK_BIT_WIDTH + ACPI_PM1B_EVT_BLK_BIT_WIDTH) / 8)
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//
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// Number of bytes decoded by PM1 control blocks (a and b)
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//
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#define ACPI_PM1_CNT_LEN ((ACPI_PM1A_CNT_BLK_BIT_WIDTH + ACPI_PM1B_CNT_BLK_BIT_WIDTH) / 8)
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//
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// Number of bytes decoded by PM2 control block
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//
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#define ACPI_PM2_CNT_LEN (ACPI_PM2_CNT_BLK_BIT_WIDTH / 8)
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//
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// Number of bytes decoded by PM timer block
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//
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#define ACPI_PM_TMR_LEN (ACPI_PM_TMR_BLK_BIT_WIDTH / 8)
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//
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// Number of bytes decoded by GPE0 block
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//
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#define ACPI_GPE0_BLK_LEN (ACPI_GPE0_BLK_BIT_WIDTH / 8)
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//
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// Number of bytes decoded by GPE1 block
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//
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#define ACPI_GPE1_BLK_LEN 0
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#endif
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