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Keir Fraser
ec9db49cf0
1) PCI_PM_CTRL_NO_SOFT_RESET: this is bit3 of PMCSR(Power Management Control/Status). It should be 8. This bit means a device's capability of not doing an internal reset across D3hot/D0. If the bit is 1, there shall be no reset across D3hot/D0, so we should not use it as a method to reset device. 2) When performing reset using standard FLR methods, we should sleep at least 100ms; in current code, it's incorrect somewhere we sleep 0.2s and somewhere 0.01s. 3) In detect_dev_info(), fix a typo: PCI_EXP_TYPE_PCI_BRIDG -> PCI_EXP_FLAGS_TYPE. 4) fix a small typo in the comment of transform_list(). Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
The file test.py here is from the Zope project, and is Copyright (c) 2001, 2002 Zope Corporation and Contributors. This file is released under the Zope Public License, version 2.0, a copy of which is in the file ZPL-2.0.