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Julien Grall
f4febe5bfb
The new helpers make it easier to read the code by abstracting the way to set/get an MFN from/to an LPAE entry. The helpers are using "walk" as the bits are common across different LPAE stages. At the same time, use the new helpers to replace the various open-coding place. Signed-off-by: Julien Grall <julien.grall@arm.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
274 lines
10 KiB
C
274 lines
10 KiB
C
#ifndef __ARM_LPAE_H__
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#define __ARM_LPAE_H__
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#ifndef __ASSEMBLY__
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#include <xen/page-defs.h>
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/*
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* WARNING! Unlike the x86 pagetable code, where l1 is the lowest level and
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* l4 is the root of the trie, the ARM pagetables follow ARM's documentation:
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* the levels are called first, second &c in the order that the MMU walks them
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* (i.e. "first" is the root of the trie).
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*/
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/******************************************************************************
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* ARMv7-A LPAE pagetables: 3-level trie, mapping 40-bit input to
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* 40-bit output addresses. Tables at all levels have 512 64-bit entries
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* (i.e. are 4Kb long).
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*
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* The bit-shuffling that has the permission bits in branch nodes in a
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* different place from those in leaf nodes seems to be to allow linear
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* pagetable tricks. If we're not doing that then the set of permission
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* bits that's not in use in a given node type can be used as
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* extra software-defined bits.
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*/
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typedef struct __packed {
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/* These are used in all kinds of entry. */
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unsigned long valid:1; /* Valid mapping */
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unsigned long table:1; /* == 1 in 4k map entries too */
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/*
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* These ten bits are only used in Block entries and are ignored
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* in Table entries.
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*/
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unsigned long ai:3; /* Attribute Index */
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unsigned long ns:1; /* Not-Secure */
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unsigned long up:1; /* Unpriviledged access */
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unsigned long ro:1; /* Read-Only */
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unsigned long sh:2; /* Shareability */
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unsigned long af:1; /* Access Flag */
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unsigned long ng:1; /* Not-Global */
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/* The base address must be appropriately aligned for Block entries */
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unsigned long long base:36; /* Base address of block or next table */
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unsigned long sbz:4; /* Must be zero */
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/*
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* These seven bits are only used in Block entries and are ignored
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* in Table entries.
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*/
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unsigned long contig:1; /* In a block of 16 contiguous entries */
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unsigned long pxn:1; /* Privileged-XN */
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unsigned long xn:1; /* eXecute-Never */
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unsigned long avail:4; /* Ignored by hardware */
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/*
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* These 5 bits are only used in Table entries and are ignored in
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* Block entries.
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*/
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unsigned long pxnt:1; /* Privileged-XN */
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unsigned long xnt:1; /* eXecute-Never */
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unsigned long apt:2; /* Access Permissions */
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unsigned long nst:1; /* Not-Secure */
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} lpae_pt_t;
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/*
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* The p2m tables have almost the same layout, but some of the permission
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* and cache-control bits are laid out differently (or missing).
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*/
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typedef struct __packed {
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/* These are used in all kinds of entry. */
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unsigned long valid:1; /* Valid mapping */
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unsigned long table:1; /* == 1 in 4k map entries too */
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/*
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* These ten bits are only used in Block entries and are ignored
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* in Table entries.
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*/
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unsigned long mattr:4; /* Memory Attributes */
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unsigned long read:1; /* Read access */
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unsigned long write:1; /* Write access */
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unsigned long sh:2; /* Shareability */
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unsigned long af:1; /* Access Flag */
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unsigned long sbz4:1;
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/* The base address must be appropriately aligned for Block entries */
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unsigned long long base:36; /* Base address of block or next table */
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unsigned long sbz3:4;
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/*
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* These seven bits are only used in Block entries and are ignored
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* in Table entries.
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*/
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unsigned long contig:1; /* In a block of 16 contiguous entries */
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unsigned long sbz2:1;
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unsigned long xn:1; /* eXecute-Never */
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unsigned long type:4; /* Ignore by hardware. Used to store p2m types */
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unsigned long sbz1:5;
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} lpae_p2m_t;
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/* Permission mask: xn, write, read */
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#define P2M_PERM_MASK (0x00400000000000C0ULL)
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#define P2M_CLEAR_PERM(pte) ((pte).bits & ~P2M_PERM_MASK)
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/*
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* Walk is the common bits of p2m and pt entries which are needed to
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* simply walk the table (e.g. for debug).
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*/
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typedef struct __packed {
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/* These are used in all kinds of entry. */
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unsigned long valid:1; /* Valid mapping */
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unsigned long table:1; /* == 1 in 4k map entries too */
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unsigned long pad2:10;
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/* The base address must be appropriately aligned for Block entries */
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unsigned long long base:36; /* Base address of block or next table */
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unsigned long pad1:16;
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} lpae_walk_t;
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typedef union {
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uint64_t bits;
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lpae_pt_t pt;
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lpae_p2m_t p2m;
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lpae_walk_t walk;
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} lpae_t;
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static inline bool lpae_is_valid(lpae_t pte)
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{
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return pte.walk.valid;
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}
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static inline bool lpae_is_table(lpae_t pte, unsigned int level)
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{
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return (level < 3) && lpae_is_valid(pte) && pte.walk.table;
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}
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static inline bool lpae_is_mapping(lpae_t pte, unsigned int level)
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{
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if ( !lpae_is_valid(pte) )
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return false;
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else if ( level == 3 )
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return pte.walk.table;
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else
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return !pte.walk.table;
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}
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static inline bool lpae_is_superpage(lpae_t pte, unsigned int level)
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{
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return (level < 3) && lpae_is_mapping(pte, level);
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}
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#define lpae_get_mfn(pte) (_mfn((pte).walk.base))
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#define lpae_set_mfn(pte, mfn) ((pte).walk.base = mfn_x(mfn))
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/*
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* AArch64 supports pages with different sizes (4K, 16K, and 64K). To enable
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* page table walks for various configurations, the following helpers enable
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* walking the translation table with varying page size granularities.
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*/
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#define LPAE_SHIFT_4K (9)
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#define LPAE_SHIFT_16K (11)
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#define LPAE_SHIFT_64K (13)
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#define lpae_entries(gran) (_AC(1,U) << LPAE_SHIFT_##gran)
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#define lpae_entry_mask(gran) (lpae_entries(gran) - 1)
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#define third_shift(gran) (PAGE_SHIFT_##gran)
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#define third_size(gran) ((paddr_t)1 << third_shift(gran))
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#define second_shift(gran) (third_shift(gran) + LPAE_SHIFT_##gran)
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#define second_size(gran) ((paddr_t)1 << second_shift(gran))
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#define first_shift(gran) (second_shift(gran) + LPAE_SHIFT_##gran)
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#define first_size(gran) ((paddr_t)1 << first_shift(gran))
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/* Note that there is no zeroeth lookup level with a 64K granule size. */
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#define zeroeth_shift(gran) (first_shift(gran) + LPAE_SHIFT_##gran)
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#define zeroeth_size(gran) ((paddr_t)1 << zeroeth_shift(gran))
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#define TABLE_OFFSET(offs, gran) (offs & lpae_entry_mask(gran))
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#define TABLE_OFFSET_HELPERS(gran) \
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static inline paddr_t third_table_offset_##gran##K(paddr_t va) \
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{ \
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return TABLE_OFFSET((va >> third_shift(gran##K)), gran##K); \
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} \
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\
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static inline paddr_t second_table_offset_##gran##K(paddr_t va) \
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{ \
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return TABLE_OFFSET((va >> second_shift(gran##K)), gran##K); \
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} \
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\
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static inline paddr_t first_table_offset_##gran##K(paddr_t va) \
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{ \
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return TABLE_OFFSET((va >> first_shift(gran##K)), gran##K); \
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} \
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\
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static inline paddr_t zeroeth_table_offset_##gran##K(paddr_t va) \
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{ \
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/* Note that there is no zeroeth lookup level with 64K granule sizes. */\
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if ( gran == 64 ) \
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return 0; \
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else \
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return TABLE_OFFSET((va >> zeroeth_shift(gran##K)), gran##K); \
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} \
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TABLE_OFFSET_HELPERS(4);
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TABLE_OFFSET_HELPERS(16);
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TABLE_OFFSET_HELPERS(64);
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#undef TABLE_OFFSET
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#undef TABLE_OFFSET_HELPERS
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#endif /* __ASSEMBLY__ */
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/*
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* These numbers add up to a 48-bit input address space.
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*
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* On 32-bit the zeroeth level does not exist, therefore the total is
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* 39-bits. The ARMv7-A architecture actually specifies a 40-bit input
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* address space for the p2m, with an 8K (1024-entry) top-level table.
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* However Xen only supports 16GB of RAM on 32-bit ARM systems and
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* therefore 39-bits are sufficient.
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*/
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#define LPAE_SHIFT 9
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#define LPAE_ENTRIES (_AC(1,U) << LPAE_SHIFT)
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#define LPAE_ENTRY_MASK (LPAE_ENTRIES - 1)
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#define THIRD_SHIFT (PAGE_SHIFT)
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#define THIRD_ORDER (THIRD_SHIFT - PAGE_SHIFT)
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#define THIRD_SIZE ((paddr_t)1 << THIRD_SHIFT)
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#define THIRD_MASK (~(THIRD_SIZE - 1))
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#define SECOND_SHIFT (THIRD_SHIFT + LPAE_SHIFT)
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#define SECOND_ORDER (SECOND_SHIFT - PAGE_SHIFT)
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#define SECOND_SIZE ((paddr_t)1 << SECOND_SHIFT)
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#define SECOND_MASK (~(SECOND_SIZE - 1))
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#define FIRST_SHIFT (SECOND_SHIFT + LPAE_SHIFT)
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#define FIRST_ORDER (FIRST_SHIFT - PAGE_SHIFT)
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#define FIRST_SIZE ((paddr_t)1 << FIRST_SHIFT)
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#define FIRST_MASK (~(FIRST_SIZE - 1))
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#define ZEROETH_SHIFT (FIRST_SHIFT + LPAE_SHIFT)
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#define ZEROETH_ORDER (ZEROETH_SHIFT - PAGE_SHIFT)
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#define ZEROETH_SIZE ((paddr_t)1 << ZEROETH_SHIFT)
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#define ZEROETH_MASK (~(ZEROETH_SIZE - 1))
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/* Calculate the offsets into the pagetables for a given VA */
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#define zeroeth_linear_offset(va) ((va) >> ZEROETH_SHIFT)
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#define first_linear_offset(va) ((va) >> FIRST_SHIFT)
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#define second_linear_offset(va) ((va) >> SECOND_SHIFT)
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#define third_linear_offset(va) ((va) >> THIRD_SHIFT)
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#define TABLE_OFFSET(offs) ((unsigned int)(offs) & LPAE_ENTRY_MASK)
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#define first_table_offset(va) TABLE_OFFSET(first_linear_offset(va))
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#define second_table_offset(va) TABLE_OFFSET(second_linear_offset(va))
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#define third_table_offset(va) TABLE_OFFSET(third_linear_offset(va))
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#define zeroeth_table_offset(va) TABLE_OFFSET(zeroeth_linear_offset(va))
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#endif /* __ARM_LPAE_H__ */
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/*
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* Local variables:
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* mode: C
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* c-file-style: "BSD"
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* c-basic-offset: 4
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* tab-width: 4
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* indent-tabs-mode: nil
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* End:
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*/
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