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iap10@labyrinth.cl.cam.ac.uk
353e94eeb8
add a handy tool for reading the P4 performance counters: xen_perfctr
560 lines
21 KiB
C
560 lines
21 KiB
C
/*
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* For P6 use PERFCTR1 (0 used for APIC NMI watchdog). Must setup after
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* APIC NMI watchdog setup. Note that if this previous setup doesn't happen
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* we still must enable both counters.
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*
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* P4 Xeon with Hyperthreading has counters per physical package which can
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* count events from either logical CPU. However, in many cases more than
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* ECSR and CCCR/counter can be used to count the same event. For instr or
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* uops retired, use either ESCR0/IQ_CCCR0 ESCR1/IQ_CCCR2.
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*
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* USE CONFIG_MPENTIUM4_HT for a P4 Xeon with hyperthreading.
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*
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* Note that the counters may be initialised on each logical processor
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* which will cause each physical processor to be initialised twice. This
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* should not cause a problem.
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*/
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#ifndef P4PERF_H
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#define P4PERF_H
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#ifdef __KERNEL__
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#include <asm/msr.h>
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#endif
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/*****************************************************************************
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* Performance counter configuration. *
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*****************************************************************************/
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#ifndef P6_EVNTSEL_OS
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# define P6_EVNTSEL_OS (1 << 17)
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# define P6_EVNTSEL_USR (1 << 16)
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# define P6_EVNTSEL_E (1 << 18)
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# define P6_EVNTSEL_EN (1 << 22)
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#endif
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#define P6_PERF_INST_RETIRED 0xc0
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#define P6_PERF_UOPS_RETIRED 0xc2
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#define P4_ESCR_USR (1 << 2)
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#define P4_ESCR_OS (1 << 3)
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#define P4_ESCR_T0_USR (1 << 2) /* First logical CPU */
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#define P4_ESCR_T0_OS (1 << 3)
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#define P4_ESCR_T1_USR (1 << 0) /* Second logical CPU */
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#define P4_ESCR_T1_OS (1 << 1)
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#define P4_ESCR_TE (1 << 4)
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#define P4_ESCR_THREADS(t) (t)
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#define P4_ESCR_TV(tag) (tag << 5)
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#define P4_ESCR_EVNTSEL(e) (e << 25)
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#define P4_ESCR_EVNTMASK(e) (e << 9)
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#define P4_ESCR_EVNTSEL_FRONT_END 0x08
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#define P4_ESCR_EVNTSEL_EXECUTION 0x0c
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#define P4_ESCR_EVNTSEL_REPLAY 0x09
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#define P4_ESCR_EVNTSEL_INSTR_RETIRED 0x02
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#define P4_ESCR_EVNTSEL_UOPS_RETIRED 0x01
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#define P4_ESCR_EVNTSEL_UOP_TYPE 0x02
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#define P4_ESCR_EVNTSEL_RET_MBR_TYPE 0x05
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//#define P4_ESCR_EVNTSEL_RET_MBR_TYPE 0x04
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#define P4_ESCR_EVNTMASK_FE_NBOGUS 0x01
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#define P4_ESCR_EVNTMASK_FE_BOGUS 0x02
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#define P4_ESCR_EVNTMASK_EXEC_NBOGUS0 0x01
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#define P4_ESCR_EVNTMASK_EXEC_NBOGUS1 0x02
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#define P4_ESCR_EVNTMASK_EXEC_NBOGUS2 0x04
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#define P4_ESCR_EVNTMASK_EXEC_NBOGUS3 0x08
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#define P4_ESCR_EVNTMASK_EXEC_BOGUS0 0x10
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#define P4_ESCR_EVNTMASK_EXEC_BOGUS1 0x20
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#define P4_ESCR_EVNTMASK_EXEC_BOGUS2 0x40
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#define P4_ESCR_EVNTMASK_EXEC_BOGUS3 0x80
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#define P4_ESCR_EVNTMASK_REPLAY_NBOGUS 0x01
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#define P4_ESCR_EVNTMASK_REPLAY_BOGUS 0x02
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#define P4_ESCR_EVNTMASK_IRET_NB_NTAG 0x01
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#define P4_ESCR_EVNTMASK_IRET_NB_TAG 0x02
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#define P4_ESCR_EVNTMASK_IRET_B_NTAG 0x04
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#define P4_ESCR_EVNTMASK_IRET_B_TAG 0x08
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#define P4_ESCR_EVNTMASK_URET_NBOGUS 0x01
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#define P4_ESCR_EVNTMASK_URET_BOGUS 0x02
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#define P4_ESCR_EVNTMASK_UOP_LOADS 0x02
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#define P4_ESCR_EVNTMASK_UOP_STORES 0x04
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#define P4_ESCR_EVNTMASK_RMBRT_COND 0x02
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#define P4_ESCR_EVNTMASK_RMBRT_CALL 0x04
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#define P4_ESCR_EVNTMASK_RMBRT_RETURN 0x08
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#define P4_ESCR_EVNTMASK_RMBRT_INDIR 0x10
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#define P4_ESCR_EVNTMASK_RBRT_COND 0x02
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#define P4_ESCR_EVNTMASK_RBRT_CALL 0x04
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#define P4_ESCR_EVNTMASK_RBRT_RETURN 0x08
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#define P4_ESCR_EVNTMASK_RBRT_INDIR 0x10
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//#define P4_ESCR_EVNTMASK_INSTR_RETIRED 0x01 /* Non bogus, not tagged */
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//#define P4_ESCR_EVNTMASK_UOPS_RETIRED 0x01 /* Non bogus */
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#define P4_CCCR_OVF (1 << 31)
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#define P4_CCCR_CASCADE (1 << 30)
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#define P4_CCCR_FORCE_OVF (1 << 25)
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#define P4_CCCR_EDGE (1 << 24)
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#define P4_CCCR_COMPLEMENT (1 << 19)
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#define P4_CCCR_COMPARE (1 << 18)
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#define P4_CCCR_THRESHOLD(t) (t << 20)
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#define P4_CCCR_ENABLE (1 << 12)
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#define P4_CCCR_ESCR(escr) (escr << 13)
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#define P4_CCCR_ACTIVE_THREAD(t) (t << 16) /* Set to 11 */
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#define P4_CCCR_OVF_PMI_T0 (1 << 26)
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#define P4_CCCR_OVF_PMI_T1 (1 << 27)
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#define P4_CCCR_RESERVED (3 << 16)
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#define P4_CCCR_OVF_PMI (1 << 26)
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// BPU
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#define MSR_P4_BPU_COUNTER0 0x300
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#define MSR_P4_BPU_COUNTER1 0x301
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#define MSR_P4_BPU_CCCR0 0x360
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#define MSR_P4_BPU_CCCR1 0x361
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#define MSR_P4_BPU_COUNTER2 0x302
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#define MSR_P4_BPU_COUNTER3 0x303
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#define MSR_P4_BPU_CCCR2 0x362
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#define MSR_P4_BPU_CCCR3 0x363
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#define MSR_P4_BSU_ESCR0 0x3a0
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#define MSR_P4_FSB_ESCR0 0x3a2
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#define MSR_P4_MOB_ESCR0 0x3aa
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#define MSR_P4_PMH_ESCR0 0x3ac
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#define MSR_P4_BPU_ESCR0 0x3b2
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#define MSR_P4_IS_ESCR0 0x3b4
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#define MSR_P4_ITLB_ESCR0 0x3b6
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#define MSR_P4_IX_ESCR0 0x3c8
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#define P4_BSU_ESCR0_NUMBER 7
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#define P4_FSB_ESCR0_NUMBER 6
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#define P4_MOB_ESCR0_NUMBER 2
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#define P4_PMH_ESCR0_NUMBER 4
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#define P4_BPU_ESCR0_NUMBER 0
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#define P4_IS_ESCR0_NUMBER 1
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#define P4_ITLB_ESCR0_NUMBER 3
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#define P4_IX_ESCR0_NUMBER 5
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#define MSR_P4_BSU_ESCR1 0x3a1
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#define MSR_P4_FSB_ESCR1 0x3a3
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#define MSR_P4_MOB_ESCR1 0x3ab
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#define MSR_P4_PMH_ESCR1 0x3ad
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#define MSR_P4_BPU_ESCR1 0x3b3
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#define MSR_P4_IS_ESCR1 0x3b5
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#define MSR_P4_ITLB_ESCR1 0x3b7
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#define MSR_P4_IX_ESCR1 0x3c9
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#define P4_BSU_ESCR1_NUMBER 7
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#define P4_FSB_ESCR1_NUMBER 6
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#define P4_MOB_ESCR1_NUMBER 2
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#define P4_PMH_ESCR1_NUMBER 4
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#define P4_BPU_ESCR1_NUMBER 0
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#define P4_IS_ESCR1_NUMBER 1
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#define P4_ITLB_ESCR1_NUMBER 3
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#define P4_IX_ESCR1_NUMBER 5
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// MS
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#define MSR_P4_MS_COUNTER0 0x304
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#define MSR_P4_MS_COUNTER1 0x305
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#define MSR_P4_MS_CCCR0 0x364
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#define MSR_P4_MS_CCCR1 0x365
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#define MSR_P4_MS_COUNTER2 0x306
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#define MSR_P4_MS_COUNTER3 0x307
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#define MSR_P4_MS_CCCR2 0x366
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#define MSR_P4_MS_CCCR3 0x367
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#define MSR_P4_MS_ESCR0 0x3c0
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#define MSR_P4_TBPU_ESCR0 0x3c2
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#define MSR_P4_TC_ESCR0 0x3c4
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#define P4_MS_ESCR0_NUMBER 0
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#define P4_TBPU_ESCR0_NUMBER 2
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#define P4_TC_ESCR0_NUMBER 1
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#define MSR_P4_MS_ESCR1 0x3c1
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#define MSR_P4_TBPU_ESCR1 0x3c3
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#define MSR_P4_TC_ESCR1 0x3c5
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#define P4_MS_ESCR1_NUMBER 0
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#define P4_TBPU_ESCR1_NUMBER 2
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#define P4_TC_ESCR1_NUMBER 1
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// FLAME
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#define MSR_P4_FLAME_COUNTER0 0x308
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#define MSR_P4_FLAME_COUNTER1 0x309
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#define MSR_P4_FLAME_CCCR0 0x368
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#define MSR_P4_FLAME_CCCR1 0x369
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#define MSR_P4_FLAME_COUNTER2 0x30a
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#define MSR_P4_FLAME_COUNTER3 0x30b
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#define MSR_P4_FLAME_CCCR2 0x36a
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#define MSR_P4_FLAME_CCCR3 0x36b
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#define MSR_P4_FIRM_ESCR0 0x3a4
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#define MSR_P4_FLAME_ESCR0 0x3a6
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#define MSR_P4_DAC_ESCR0 0x3a8
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#define MSR_P4_SAAT_ESCR0 0x3ae
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#define MSR_P4_U2L_ESCR0 0x3b0
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#define P4_FIRM_ESCR0_NUMBER 1
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#define P4_FLAME_ESCR0_NUMBER 0
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#define P4_DAC_ESCR0_NUMBER 5
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#define P4_SAAT_ESCR0_NUMBER 2
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#define P4_U2L_ESCR0_NUMBER 3
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#define MSR_P4_FIRM_ESCR1 0x3a5
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#define MSR_P4_FLAME_ESCR1 0x3a7
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#define MSR_P4_DAC_ESCR1 0x3a9
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#define MSR_P4_SAAT_ESCR1 0x3af
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#define MSR_P4_U2L_ESCR1 0x3b1
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#define P4_FIRM_ESCR1_NUMBER 1
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#define P4_FLAME_ESCR1_NUMBER 0
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#define P4_DAC_ESCR1_NUMBER 5
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#define P4_SAAT_ESCR1_NUMBER 2
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#define P4_U2L_ESCR1_NUMBER 3
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// IQ
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#define MSR_P4_IQ_COUNTER0 0x30c
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#define MSR_P4_IQ_COUNTER1 0x30d
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#define MSR_P4_IQ_CCCR0 0x36c
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#define MSR_P4_IQ_CCCR1 0x36d
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#define MSR_P4_IQ_COUNTER2 0x30e
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#define MSR_P4_IQ_COUNTER3 0x30f
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#define MSR_P4_IQ_CCCR2 0x36e
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#define MSR_P4_IQ_CCCR3 0x36f
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#define MSR_P4_IQ_COUNTER4 0x310
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#define MSR_P4_IQ_COUNTER5 0x311
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#define MSR_P4_IQ_CCCR4 0x370
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#define MSR_P4_IQ_CCCR5 0x371
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#define MSR_P4_CRU_ESCR0 0x3b8
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#define MSR_P4_CRU_ESCR2 0x3cc
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#define MSR_P4_CRU_ESCR4 0x3e0
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#define MSR_P4_IQ_ESCR0 0x3ba
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#define MSR_P4_RAT_ESCR0 0x3bc
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#define MSR_P4_SSU_ESCR0 0x3be
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#define MSR_P4_ALF_ESCR0 0x3ca
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#define P4_CRU_ESCR0_NUMBER 4
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#define P4_CRU_ESCR2_NUMBER 5
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#define P4_CRU_ESCR4_NUMBER 6
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#define P4_IQ_ESCR0_NUMBER 0
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#define P4_RAT_ESCR0_NUMBER 2
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#define P4_SSU_ESCR0_NUMBER 3
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#define P4_ALF_ESCR0_NUMBER 1
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#define MSR_P4_CRU_ESCR1 0x3b9
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#define MSR_P4_CRU_ESCR3 0x3cd
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#define MSR_P4_CRU_ESCR5 0x3e1
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#define MSR_P4_IQ_ESCR1 0x3bb
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#define MSR_P4_RAT_ESCR1 0x3bd
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#define MSR_P4_ALF_ESCR1 0x3cb
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#define P4_CRU_ESCR1_NUMBER 4
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#define P4_CRU_ESCR3_NUMBER 5
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#define P4_CRU_ESCR5_NUMBER 6
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#define P4_IQ_ESCR1_NUMBER 0
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#define P4_RAT_ESCR1_NUMBER 2
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#define P4_ALF_ESCR1_NUMBER 1
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#define P4_BPU_COUNTER0_NUMBER 0
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#define P4_BPU_COUNTER1_NUMBER 1
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#define P4_BPU_COUNTER2_NUMBER 2
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#define P4_BPU_COUNTER3_NUMBER 3
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#define P4_MS_COUNTER0_NUMBER 4
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#define P4_MS_COUNTER1_NUMBER 5
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#define P4_MS_COUNTER2_NUMBER 6
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#define P4_MS_COUNTER3_NUMBER 7
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#define P4_FLAME_COUNTER0_NUMBER 8
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#define P4_FLAME_COUNTER1_NUMBER 9
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#define P4_FLAME_COUNTER2_NUMBER 10
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#define P4_FLAME_COUNTER3_NUMBER 11
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#define P4_IQ_COUNTER0_NUMBER 12
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#define P4_IQ_COUNTER1_NUMBER 13
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#define P4_IQ_COUNTER2_NUMBER 14
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#define P4_IQ_COUNTER3_NUMBER 15
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#define P4_IQ_COUNTER4_NUMBER 16
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#define P4_IQ_COUNTER5_NUMBER 17
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/* PEBS
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*/
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#define MSR_P4_PEBS_ENABLE 0x3F1
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#define MSR_P4_PEBS_MATRIX_VERT 0x3F2
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#define P4_PEBS_ENABLE_MY_THR (1 << 25)
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#define P4_PEBS_ENABLE_OTH_THR (1 << 26)
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#define P4_PEBS_ENABLE (1 << 24)
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#define P4_PEBS_BIT0 (1 << 0)
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#define P4_PEBS_BIT1 (1 << 1)
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#define P4_PEBS_BIT2 (1 << 2)
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#define P4_PEBS_MATRIX_VERT_BIT0 (1 << 0)
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#define P4_PEBS_MATRIX_VERT_BIT1 (1 << 1)
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#define P4_PEBS_MATRIX_VERT_BIT2 (1 << 2)
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/* Replay tagging.
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*/
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#define P4_REPLAY_TAGGING_PEBS_L1LMR P4_PEBS_BIT0
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#define P4_REPLAY_TAGGING_PEBS_L2LMR P4_PEBS_BIT1
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#define P4_REPLAY_TAGGING_PEBS_DTLMR P4_PEBS_BIT2
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#define P4_REPLAY_TAGGING_PEBS_DTSMR P4_PEBS_BIT2
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#define P4_REPLAY_TAGGING_PEBS_DTAMR P4_PEBS_BIT2
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#define P4_REPLAY_TAGGING_VERT_L1LMR P4_PEBS_MATRIX_VERT_BIT0
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#define P4_REPLAY_TAGGING_VERT_L2LMR P4_PEBS_MATRIX_VERT_BIT0
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#define P4_REPLAY_TAGGING_VERT_DTLMR P4_PEBS_MATRIX_VERT_BIT0
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#define P4_REPLAY_TAGGING_VERT_DTSMR P4_PEBS_MATRIX_VERT_BIT1
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#define P4_REPLAY_TAGGING_VERT_DTAMR P4_PEBS_MATRIX_VERT_BIT0 | P4_PEBS_MATRIX_VERT_BIT1
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/*****************************************************************************
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* *
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*****************************************************************************/
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// x87_FP_uop
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#define EVENT_SEL_x87_FP_uop 0x04
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#define EVENT_MASK_x87_FP_uop_ALL (1 << 15)
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// execution event (at retirement)
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#define EVENT_SEL_execution_event 0x0C
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// scalar_SP_uop
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#define EVENT_SEL_scalar_SP_uop 0x0a
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#define EVENT_MASK_scalar_SP_uop_ALL (1 << 15)
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// scalar_DP_uop
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#define EVENT_SEL_scalar_DP_uop 0x0e
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#define EVENT_MASK_scalar_DP_uop_ALL (1 << 15)
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// Instruction retired
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#define EVENT_SEL_instr_retired 0x02
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#define EVENT_MASK_instr_retired_ALL 0x0f
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// uOps retired
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#define EVENT_SEL_uops_retired 0x01
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#define EVENT_MASK_uops_retired_ALL 0x03
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// L1 misses retired
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#define EVENT_SEL_replay_event 0x09
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#define EVENT_MASK_replay_event_ALL 0x03
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// Trace cache
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#define EVENT_SEL_BPU_fetch_request 0x03
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#define EVENT_MASK_BPU_fetch_request_TCMISS 0x01
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// Bus activity
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#define EVENT_SEL_FSB_data_activity 0x17
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#define EVENT_MASK_FSB_data_activity_DRDY_DRV 0x01
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#define EVENT_MASK_FSB_data_activity_DRDY_OWN 0x02
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#define EVENT_MASK_FSB_data_activity_DRDY_OOTHER 0x04
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#define EVENT_MASK_FSB_data_activity_DBSY_DRV 0x08
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#define EVENT_MASK_FSB_data_activity_DBSY_OWN 0x10
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#define EVENT_MASK_FSB_data_activity_DBSY_OOTHER 0x20
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// Cache L2
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#define EVENT_SEL_BSQ_cache_reference 0x0c
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#define EVENT_MASK_BSQ_cache_reference_RD_L2_HITS 0x001
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#define EVENT_MASK_BSQ_cache_reference_RD_L2_HITE 0x002
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#define EVENT_MASK_BSQ_cache_reference_RD_L2_HITM 0x004
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#define EVENT_MASK_BSQ_cache_reference_RD_L3_HITS 0x008
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#define EVENT_MASK_BSQ_cache_reference_RD_L3_HITE 0x010
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#define EVENT_MASK_BSQ_cache_reference_RD_L3_HITM 0x020
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#define EVENT_MASK_BSQ_cache_reference_RD_L2_MISS 0x100
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#define EVENT_MASK_BSQ_cache_reference_RD_L3_MISS 0x200
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#define EVENT_MASK_BSQ_cache_reference_WR_L2_MISS 0x400
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/*****************************************************************************
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* *
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*****************************************************************************/
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/* The following turn configuration macros into 1/0 to allow code to be
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* selected using if(MPENTIUM4_HT) rather then #ifdef (to avoid stale code).
|
|
* We rely on the compiler to optimise out unreachable code,
|
|
*/
|
|
#ifdef CONFIG_MPENTIUM4_HT
|
|
# define MPENTIUM4_HT 1
|
|
#else
|
|
# define MPENTIUM4_HT 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_MPENTIUMIII
|
|
# define MPENTIUMIII 1
|
|
#else
|
|
# define MPENTIUMIII 0
|
|
#endif
|
|
|
|
#ifdef CONFIG_MPENTIUM4
|
|
# define MPENTIUM4 1
|
|
#else
|
|
# define MPENTIUM4 0
|
|
#endif
|
|
|
|
/*****************************************************************************
|
|
* MSR access macros *
|
|
*****************************************************************************/
|
|
|
|
/* rpcc: get full 64-bit Pentium TSC value
|
|
*/
|
|
static __inline__ unsigned long long int rpcc(void)
|
|
{
|
|
unsigned int __h, __l;
|
|
__asm__ __volatile__ ("rdtsc" :"=a" (__l), "=d" (__h));
|
|
return (((unsigned long long)__h) << 32) + __l;
|
|
}
|
|
|
|
/*****************************************************************************
|
|
* Functions. *
|
|
*****************************************************************************/
|
|
|
|
#ifdef __KERNEL__
|
|
static inline void smt_sched_setup(void)
|
|
{
|
|
if (MPENTIUMIII) {
|
|
unsigned int evntsel, x;
|
|
|
|
/* Make sure counters enabled. */
|
|
rdmsr(MSR_P6_EVNTSEL0, evntsel, x);
|
|
evntsel |= P6_EVNTSEL_EN;
|
|
wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
|
|
|
|
evntsel =
|
|
P6_PERF_INST_RETIRED |
|
|
P6_EVNTSEL_OS |
|
|
P6_EVNTSEL_USR |
|
|
P6_EVNTSEL_E;
|
|
wrmsr(MSR_P6_EVNTSEL1, evntsel, 0);
|
|
}
|
|
|
|
if(MPENTIUM4) {
|
|
unsigned int x;
|
|
|
|
/* Program the ESCR */
|
|
x = P4_ESCR_USR |
|
|
P4_ESCR_OS |
|
|
P4_ESCR_EVNTSEL(P4_ESCR_EVNTSEL_INSTR_RETIRED) |
|
|
P4_ESCR_EVNTMASK(P4_ESCR_EVNTMASK_IRET_NB_NTAG);
|
|
wrmsr(MSR_P4_CRU_ESCR0, x, 0);
|
|
|
|
/* Program the CCCR */
|
|
if (MPENTIUM4_HT) {
|
|
x = P4_CCCR_ENABLE |
|
|
P4_CCCR_ESCR(P4_CRU_ESCR0_NUMBER) |
|
|
P4_CCCR_ACTIVE_THREAD(3);
|
|
}
|
|
else {
|
|
x = P4_CCCR_ENABLE |
|
|
P4_CCCR_ESCR(P4_CRU_ESCR0_NUMBER) |
|
|
P4_CCCR_RESERVED;
|
|
}
|
|
wrmsr(MSR_P4_IQ_CCCR0, x, 0);
|
|
|
|
if (MPENTIUM4_HT) {
|
|
|
|
/* Program the second ESCR */
|
|
x = P4_ESCR_T1_USR |
|
|
P4_ESCR_T1_OS |
|
|
P4_ESCR_EVNTSEL(P4_ESCR_EVNTSEL_INSTR_RETIRED) |
|
|
P4_ESCR_EVNTMASK(P4_ESCR_EVNTMASK_IRET_NB_NTAG);
|
|
wrmsr(MSR_P4_CRU_ESCR1, x, 0);
|
|
|
|
/* Program the second CCCR */
|
|
x = P4_CCCR_ENABLE |
|
|
P4_CCCR_ESCR(P4_CRU_ESCR1_NUMBER) |
|
|
P4_CCCR_ACTIVE_THREAD(3);
|
|
wrmsr(MSR_P4_IQ_CCCR2, x, 0);
|
|
}
|
|
}
|
|
|
|
if (!MPENTIUMIII && !MPENTIUM4) {
|
|
printk("WARNING: Not setting up IPC performance counters.\n");
|
|
} else {
|
|
printk("Setting up IPC performance counters.\n");
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_MPENTIUMIII
|
|
# define MY_MSR_COUNTER MSR_P6_PERFCTR1
|
|
#endif
|
|
#ifdef CONFIG_MPENTIUM4
|
|
# define MY_MSR_COUNTER MSR_P4_IQ_COUNTER0
|
|
#endif
|
|
#ifndef MY_MSR_COUNTER
|
|
# define MY_MSR_COUNTER 0 /* Never used but ensures compilation */
|
|
#endif
|
|
#define MY_MSR_COUNTER0 MSR_P4_IQ_COUNTER0
|
|
#define MY_MSR_COUNTER1 MSR_P4_IQ_COUNTER2
|
|
|
|
# define smt_sched_start_sample(task) \
|
|
{ \
|
|
unsigned int l, h; \
|
|
\
|
|
if (MPENTIUM4_HT) { \
|
|
unsigned int msr = \
|
|
(task->processor & 1)?MY_MSR_COUNTER1:MY_MSR_COUNTER0; \
|
|
rdmsr(msr, l, h); \
|
|
} \
|
|
else { \
|
|
rdmsr(MY_MSR_COUNTER, l, h); \
|
|
} \
|
|
task->ipc_sample_start_count_lo = l; \
|
|
task->ipc_sample_start_count_hi = h; \
|
|
rdtsc(l, h); \
|
|
task->ipc_sample_start_cycle_lo = l; \
|
|
task->ipc_sample_start_cycle_hi = h; \
|
|
}
|
|
|
|
# define smt_sched_stop_sample(task) \
|
|
{ \
|
|
if (task->ipc_sample_start_cycle_hi != 0) \
|
|
{ \
|
|
unsigned int cl, ch, tl, th; \
|
|
unsigned int c, t; \
|
|
\
|
|
if (MPENTIUM4_HT) { \
|
|
unsigned int msr = \
|
|
(task->processor & 1)?MY_MSR_COUNTER1:MY_MSR_COUNTER0; \
|
|
rdmsr(msr, cl, ch); \
|
|
} \
|
|
else { \
|
|
rdmsr(MY_MSR_COUNTER, cl, ch); \
|
|
} \
|
|
\
|
|
rdtsc(tl, th); \
|
|
\
|
|
c = cl - task->ipc_sample_start_count_lo; \
|
|
t = tl - task->ipc_sample_start_cycle_lo; \
|
|
task->ipc_average = IPC_AVERAGE(task->ipc_average, \
|
|
((double)c)/((double)t)); \
|
|
task->ipc_sample_start_cycle_hi = 0; \
|
|
\
|
|
} \
|
|
else \
|
|
task->ipc_average = 0.0; \
|
|
\
|
|
}
|
|
|
|
// task->ipc_sample_latest =
|
|
// (unsigned int)(1000.0*((double)c)/((double)t));
|
|
#endif /* __KERNEL__ */
|
|
|
|
|
|
#endif /* P4PERF_H */
|
|
|
|
/* End of $RCSfile$ */
|