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x86/VPMU: use pre-computed masks when checking validity of MSRs
No need to compute those masks on every MSR access. Also, when checking MSR_P6_EVNTSELx registers make sure that bit 21 (which is a reserved bit) is not set. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Acked-by: Kevin Tian <kevin.tian@intel.com> Reviewed-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
This commit is contained in:
Boris Ostrovsky authored and 
Jan Beulich committed
1 parent
a46edd2f1c
commit
00f4e7bf91
1 file changed
+18
-10
@@ -80,9 +80,16 @@ static bool_t __read_mostly full_width_write;
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#define FIXED_CTR_CTRL_BITS 4
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#define FIXED_CTR_CTRL_MASK ((1 << FIXED_CTR_CTRL_BITS) - 1)
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#define ARCH_CNTR_ENABLED (1ULL << 22)
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/* Number of general-purpose and fixed performance counters */
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static unsigned int __read_mostly arch_pmc_cnt, fixed_pmc_cnt;
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/* Masks used for testing whether and MSR is valid */
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#define ARCH_CTRL_MASK (~((1ull << 32) - 1) | (1ull << 21))
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static uint64_t __read_mostly fixed_ctrl_mask, fixed_counters_mask;
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static uint64_t __read_mostly global_ovf_ctrl_mask;
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/*
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* QUIRK to workaround an issue on various family 6 cpus.
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* The issue leads to endless PMC interrupt loops on the processor.
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@@ -479,9 +486,7 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
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ASSERT(!supported);
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if ( type == MSR_TYPE_COUNTER &&
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(msr_content &
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~((1ull << core2_get_bitwidth_fix_count()) - 1)) )
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if ( (type == MSR_TYPE_COUNTER) && (msr_content & fixed_counters_mask) )
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/* Writing unsupported bits to a fixed counter */
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return -EINVAL;
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@@ -490,9 +495,7 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
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switch ( msr )
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{
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case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
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if ( msr_content & ~(0xC000000000000000 |
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(((1ULL << fixed_pmc_cnt) - 1) << 32) |
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((1ULL << arch_pmc_cnt) - 1)) )
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if ( msr_content & global_ovf_ctrl_mask )
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return -EINVAL;
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core2_vpmu_cxt->global_status &= ~msr_content;
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wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, msr_content);
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@@ -526,8 +529,7 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
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core2_vpmu_cxt->global_ctrl = msr_content;
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break;
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case MSR_CORE_PERF_FIXED_CTR_CTRL:
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if ( msr_content &
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( ~((1ull << (fixed_pmc_cnt * FIXED_CTR_CTRL_BITS)) - 1)) )
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if ( msr_content & fixed_ctrl_mask )
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return -EINVAL;
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if ( has_hvm_container_vcpu(v) )
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@@ -556,7 +558,7 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
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struct xen_pmu_cntr_pair *xen_pmu_cntr_pair =
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vpmu_reg_pointer(core2_vpmu_cxt, arch_counters);
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if ( msr_content & (~((1ull << 32) - 1)) )
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if ( msr_content & ARCH_CTRL_MASK )
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return -EINVAL;
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if ( has_hvm_container_vcpu(v) )
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@@ -565,7 +567,7 @@ static int core2_vpmu_do_wrmsr(unsigned int msr, uint64_t msr_content,
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else
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rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, core2_vpmu_cxt->global_ctrl);
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if ( msr_content & (1ULL << 22) )
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if ( msr_content & ARCH_CNTR_ENABLED )
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*enabled_cntrs |= 1ULL << tmp;
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else
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*enabled_cntrs &= ~(1ULL << tmp);
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@@ -915,6 +917,12 @@ int __init core2_vpmu_init(void)
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rdmsrl(MSR_IA32_PERF_CAPABILITIES, caps);
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full_width_write = (caps >> 13) & 1;
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fixed_ctrl_mask = ~((1ull << (fixed_pmc_cnt * FIXED_CTR_CTRL_BITS)) - 1);
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fixed_counters_mask = ~((1ull << core2_get_bitwidth_fix_count()) - 1);
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global_ovf_ctrl_mask = ~(0xC000000000000000 |
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(((1ULL << fixed_pmc_cnt) - 1) << 32) |
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((1ULL << arch_pmc_cnt) - 1));
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check_pmc_quirk();
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if ( sizeof(struct xen_pmu_data) + sizeof(uint64_t) * fixed_pmc_cnt +
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