xen/arm: mm: Clear boot pagetables before bringing-up each secondary CPU

At the moment, boot pagetables are only cleared once at boot. This means
when booting CPU2 (and onwards) then boot pagetables will not be
cleared.

To keep the interface exactly the same for all secondary CPU, the boot
pagetables are now cleared before bringing-up each secondary CPU.

Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Release-acked-by: Juergen Gross <jgross@suse.com>
This commit is contained in:
Julien Grall committed 2019-10-16 12:28:26 +01:00
1 parent 4c555ec758
commit 00fc9004be
1 file changed
+19 -10
+19 -10
View File
@@ -707,16 +707,6 @@ void __init setup_pagetables(unsigned long boot_phys_offset)
switch_ttbr(ttbr);
/* Clear the copy of the boot pagetables. Each secondary CPU
* rebuilds these itself (see head.S) */
clear_table(boot_pgtable);
#ifdef CONFIG_ARM_64
clear_table(boot_first);
clear_table(boot_first_id);
#endif
clear_table(boot_second);
clear_table(boot_third);
xen_pt_enforce_wnx();
#ifdef CONFIG_ARM_32
@@ -725,9 +715,26 @@ void __init setup_pagetables(unsigned long boot_phys_offset)
#endif
}
static void clear_boot_pagetables(void)
{
/*
* Clear the copy of the boot pagetables. Each secondary CPU
* rebuilds these itself (see head.S).
*/
clear_table(boot_pgtable);
#ifdef CONFIG_ARM_64
clear_table(boot_first);
clear_table(boot_first_id);
#endif
clear_table(boot_second);
clear_table(boot_third);
}
#ifdef CONFIG_ARM_64
int init_secondary_pagetables(int cpu)
{
clear_boot_pagetables();
/* Set init_ttbr for this CPU coming up. All CPus share a single setof
* pagetables, but rewrite it each time for consistency with 32 bit. */
init_ttbr = (uintptr_t) xen_pgtable + phys_offset;
@@ -770,6 +777,8 @@ int init_secondary_pagetables(int cpu)
per_cpu(xen_pgtable, cpu) = first;
per_cpu(xen_dommap, cpu) = domheap;
clear_boot_pagetables();
/* Set init_ttbr for this CPU coming up */
init_ttbr = __pa(first);
clean_dcache(init_ttbr);
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