x86: Backport CPUID feature passthroughs from xen-unstable

Enable RDWRGSFS feature support for HVM guests

Write/read FS/GS base instructions enable user level code to
read/write FS & GS segment base registers for thread local storage.

Signed-off-by: Yang, Wei <wei.y.yang@intel.com>
xen-unstable changeset:   23539:8c75f35d55f6
xen-unstable date:        Wed Jun 15 16:06:48 2011 +0100

x86: Pass through ERMS CPUID feature for HVM and PV guests

This patch exposes ERMS feature to HVM and PV guests.

The REP MOVSB/STOSB instruction can enhance fast strings attempts to
move as much of the data with larger size load/stores as possible.

Signed-off-by: Yang, Wei <wei.y.yang@intel.com>
xen-unstable changeset:   23516:f4a47275aebf
xen-unstable date:        Tue Jun 14 13:13:18 2011 +0100

x86/hvm: Make DRNG feature visible in CPUID

This patch exposes DRNG feature to HVM guests.

The RDRAND instruction can provide software with sequences of
random numbers generated from white noise.

Signed-off-by: Yang, Wei <wei.y.yang@intel.com>
xen-unstable changeset:   23510:864a3dd1d9b4
xen-unstable date:        Tue Jun 14 12:44:48 2011 +0100

tools/libxc/xc_cpufeature.h

@@ -106,6 +106,7 @@
 #define X86_FEATURE_XSAVE	(4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
 #define X86_FEATURE_AVX		(4*32+28) /* Advanced Vector Extensions */
 #define X86_FEATURE_F16C	(4*32+29) /* Half-precision convert instruction */
+#define X86_FEATURE_RDRAND      (4*32+30) /* Digital Random Number Generator */
 #define X86_FEATURE_HYPERVISOR	(4*32+31) /* Running under some hypervisor */
 
 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
@@ -144,5 +145,6 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
 #define X86_FEATURE_FSGSBASE	(7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
 #define X86_FEATURE_SMEP        (7*32+ 7) /* Supervisor Mode Execution Protection */
+#define X86_FEATURE_ERMS        (7*32+ 9) /* Enhanced REP MOVSB/STOSB */
 
 #endif /* __LIBXC_CPUFEATURE_H */

tools/libxc/xc_cpuid_x86.c

@@ -262,6 +262,7 @@ static void xc_cpuid_hvm_policy(
                     bitmaskof(X86_FEATURE_POPCNT) |
                     bitmaskof(X86_FEATURE_AES) |
                     bitmaskof(X86_FEATURE_F16C) |
+                    bitmaskof(X86_FEATURE_RDRAND) |
                     ((xfeature_mask != 0) ?
                      (bitmaskof(X86_FEATURE_AVX) |
                       bitmaskof(X86_FEATURE_XSAVE)) : 0));
@@ -302,7 +303,9 @@ static void xc_cpuid_hvm_policy(
 
     case 0x00000007: /* Intel-defined CPU features */
         if ( input[1] == 0 ) {
-            regs[1] &= bitmaskof(X86_FEATURE_SMEP);
+            regs[1] &= (bitmaskof(X86_FEATURE_SMEP) |
+                        bitmaskof(X86_FEATURE_ERMS) |
+                        bitmaskof(X86_FEATURE_FSGSBASE));
         } else
             regs[1] = 0;
         regs[0] = regs[2] = regs[3] = 0;
@@ -424,7 +427,8 @@ static void xc_cpuid_pv_policy(
 
     case 7:
         if ( input[1] == 0 )
-            regs[1] &= bitmaskof(X86_FEATURE_FSGSBASE);
+            regs[1] &= (bitmaskof(X86_FEATURE_FSGSBASE) |
+                        bitmaskof(X86_FEATURE_ERMS));
         else
             regs[1] = 0;
         regs[0] = regs[2] = regs[3] = 0;

xen/arch/x86/traps.c

@@ -782,7 +782,8 @@ static void pv_cpuid(struct cpu_user_regs *regs)
         break;
     case 7:
         if ( regs->ecx == 0 )
-            b &= cpufeat_mask(X86_FEATURE_FSGSBASE);
+            b &= (cpufeat_mask(X86_FEATURE_FSGSBASE) |
+                  cpufeat_mask(X86_FEATURE_ERMS));
         else
             b = 0;
         a = c = d = 0;

xen/include/asm-x86/cpufeature.h

@@ -105,6 +105,7 @@
 #define X86_FEATURE_OSXSAVE	(4*32+27) /* OSXSAVE */
 #define X86_FEATURE_AVX 	(4*32+28) /* Advanced Vector Extensions */
 #define X86_FEATURE_F16C 	(4*32+29) /* Half-precision convert instruction */
+#define X86_FEATURE_RDRAND 	(4*32+30) /* Digital Random Number Generator */
 #define X86_FEATURE_HYPERVISOR	(4*32+31) /* Running under some hypervisor */
 
 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
@@ -143,6 +144,7 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 7 */
 #define X86_FEATURE_FSGSBASE	(7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
 #define X86_FEATURE_SMEP	(7*32+ 7) /* Supervisor Mode Execution Protection */
+#define X86_FEATURE_ERMS	(7*32+ 9) /* Enhanced REP MOVSB/STOSB */
 
 #define cpu_has(c, bit)		test_bit(bit, (c)->x86_capability)
 #define boot_cpu_has(bit)	test_bit(bit, boot_cpu_data.x86_capability)

xen/include/asm-x86/hvm/hvm.h

@@ -294,6 +294,7 @@ static inline int hvm_do_pmu_interrupt(struct cpu_user_regs *regs)
         X86_CR4_MCE | X86_CR4_PGE | X86_CR4_PCE |       \
         X86_CR4_OSFXSR | X86_CR4_OSXMMEXCPT |           \
         (cpu_has_smep ? X86_CR4_SMEP : 0) |             \
+        (cpu_has_fsgsbase ? X86_CR4_FSGSBASE : 0) |     \
         (xsave_enabled(_v) ? X86_CR4_OSXSAVE : 0))))
 
 /* These exceptions must always be intercepted. */