xen/x86: add some cr3 helpers

Add some helper macros to access the address and pcid parts of cr3.

Use those helpers where appropriate.

Signed-off-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
This commit is contained in:
Juergen Gross authored and Jan Beulich committed 2018-05-29 10:19:40 +02:00
1 parent 266d5118ae
commit 0954b1107d
3 files changed
+19 -2

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+1 -1
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@@ -99,7 +99,7 @@ dbg_pv_va2mfn(dbgva_t vaddr, struct domain *dp, uint64_t pgd3val)
l2_pgentry_t l2e, *l2t;
l1_pgentry_t l1e, *l1t;
unsigned long cr3 = (pgd3val ? pgd3val : dp->vcpu[0]->arch.cr3);
mfn_t mfn = _mfn(cr3 >> PAGE_SHIFT);
mfn_t mfn = _mfn(paddr_to_pfn(cr3_pa(cr3)));
DBGP2("vaddr:%lx domid:%d cr3:%lx pgd3:%lx\n", vaddr, dp->domain_id,
cr3, pgd3val);
+1 -1
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@@ -50,7 +50,7 @@ static inline struct vcpu *mapcache_current_vcpu(void)
if ( (v = idle_vcpu[smp_processor_id()]) == current )
sync_local_execstate();
/* We must now be running on the idle page table. */
ASSERT(read_cr3() == __pa(idle_pg_table));
ASSERT(cr3_pa(read_cr3()) == __pa(idle_pg_table));
}
return v;
+17
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@@ -68,6 +68,13 @@
#define X86_CR0_CD 0x40000000 /* Cache Disable (RW) */
#define X86_CR0_PG 0x80000000 /* Paging (RW) */
/*
* Intel CPU flags in CR3
*/
#define X86_CR3_NOFLUSH (_AC(1, ULL) << 63)
#define X86_CR3_ADDR_MASK (PAGE_MASK & PADDR_MASK)
#define X86_CR3_PCID_MASK _AC(0x0fff, ULL) /* Mask for PCID */
/*
* Intel CPU features in CR4
*/
@@ -346,6 +353,16 @@ static inline void write_cr3(unsigned long val)
asm volatile ( "mov %0, %%cr3" : : "r" (val) : "memory" );
}
static inline unsigned long cr3_pa(unsigned long cr3)
{
return cr3 & X86_CR3_ADDR_MASK;
}
static inline unsigned long cr3_pcid(unsigned long cr3)
{
return cr3 & X86_CR3_PCID_MASK;
}
static inline unsigned long read_cr4(void)
{
return get_cpu_info()->cr4;
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