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x86emul: don't open code EFLAGS handling for 2-operand IMUL
Slightly extending the emulate_2op*() macro machinery makes it usable for IMUL r,r/m too, which has the benefit of smaller source code and the EFLAGS output being guaranteed to match actual hardware behavior. Signed-off-by: Jan Beulich <jbeulich@suse.com> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
This commit is contained in:
Jan Beulich committed
1 parent
a3db233ede
commit
0cf612cd0e
1 file changed
+23
-41
@@ -465,28 +465,29 @@ typedef union {
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"orl %"_LO32 _tmp",%"_LO32 _sav"; "
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/* Raw emulation: instruction has two explicit operands. */
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#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy)\
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#define __emulate_2op_nobyte(_op,_src,_dst,_eflags, wsx,wsy,wdx,wdy, \
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lsx,lsy,ldx,ldy, qsx,qsy,qdx,qdy) \
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do{ unsigned long _tmp; \
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switch ( (_dst).bytes ) \
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{ \
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case 2: \
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asm volatile ( \
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_PRE_EFLAGS("0","4","2") \
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_op"w %"_wx"3,%1; " \
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_op"w %"wsx"3,%"wdx"1; " \
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_POST_EFLAGS("0","4","2") \
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: "+g" (_eflags), "+m" ((_dst).val), "=&r" (_tmp) \
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: _wy ((_src).val), "i" (EFLAGS_MASK) ); \
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: "+g" (_eflags), "+" wdy ((_dst).val), "=&r" (_tmp) \
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: wsy ((_src).val), "i" (EFLAGS_MASK) ); \
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break; \
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case 4: \
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asm volatile ( \
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_PRE_EFLAGS("0","4","2") \
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_op"l %"_lx"3,%1; " \
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_op"l %"lsx"3,%"ldx"1; " \
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_POST_EFLAGS("0","4","2") \
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: "+g" (_eflags), "+m" ((_dst).val), "=&r" (_tmp) \
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: _ly ((_src).val), "i" (EFLAGS_MASK) ); \
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: "+g" (_eflags), "+" ldy ((_dst).val), "=&r" (_tmp) \
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: lsy ((_src).val), "i" (EFLAGS_MASK) ); \
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break; \
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case 8: \
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__emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy); \
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__emulate_2op_8byte(_op, _src, _dst, _eflags, qsx, qsy, qdx, qdy); \
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break; \
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} \
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} while (0)
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@@ -503,7 +504,8 @@ do{ unsigned long _tmp; \
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: _by ((_src).val), "i" (EFLAGS_MASK) ); \
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break; \
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default: \
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__emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy);\
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__emulate_2op_nobyte(_op,_src,_dst,_eflags, _wx,_wy,"","m", \
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_lx,_ly,"","m", _qx,_qy,"","m"); \
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break; \
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} \
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} while (0)
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@@ -517,8 +519,12 @@ do{ unsigned long _tmp; \
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"b", "q", "w", "r", _LO32, "r", "", "r")
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/* Source operand is word, long or quad sized. */
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#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
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__emulate_2op_nobyte(_op, _src, _dst, _eflags, \
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"w", "r", _LO32, "r", "", "r")
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__emulate_2op_nobyte(_op, _src, _dst, _eflags, "w", "r", "", "m", \
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_LO32, "r", "", "m", "", "r", "", "m")
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/* Operands are word, long or quad sized and source may be in memory. */
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#define emulate_2op_SrcV_srcmem(_op, _src, _dst, _eflags) \
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__emulate_2op_nobyte(_op, _src, _dst, _eflags, "", "m", "w", "r", \
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"", "m", _LO32, "r", "", "m", "", "r")
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/* Instruction has only one explicit operand (no source operand). */
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#define emulate_1op(_op,_dst,_eflags) \
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@@ -557,13 +563,13 @@ do{ unsigned long _tmp; \
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/* Emulate an instruction with quadword operands (x86/64 only). */
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#if defined(__x86_64__)
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#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
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#define __emulate_2op_8byte(_op, _src, _dst, _eflags, qsx, qsy, qdx, qdy) \
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do{ asm volatile ( \
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_PRE_EFLAGS("0","4","2") \
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_op"q %"_qx"3,%1; " \
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_op"q %"qsx"3,%"qdx"1; " \
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_POST_EFLAGS("0","4","2") \
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: "+g" (_eflags), "+m" ((_dst).val), "=&r" (_tmp) \
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: _qy ((_src).val), "i" (EFLAGS_MASK) ); \
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: "+g" (_eflags), "+" qdy ((_dst).val), "=&r" (_tmp) \
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: qsy ((_src).val), "i" (EFLAGS_MASK) ); \
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} while (0)
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#define __emulate_1op_8byte(_op, _dst, _eflags) \
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do{ asm volatile ( \
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@@ -574,7 +580,7 @@ do{ asm volatile ( \
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: "i" (EFLAGS_MASK) ); \
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} while (0)
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#elif defined(__i386__)
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#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
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#define __emulate_2op_8byte(_op, _src, _dst, _eflags, qsx, qsy, qdx, qdy)
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#define __emulate_1op_8byte(_op, _dst, _eflags)
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#endif /* __i386__ */
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@@ -4569,31 +4575,7 @@ x86_emulate(
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break;
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case 0xaf: /* imul */
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_regs.eflags &= ~(EFLG_OF|EFLG_CF);
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switch ( dst.bytes )
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{
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case 2:
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dst.val = ((uint32_t)(int16_t)src.val *
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(uint32_t)(int16_t)dst.val);
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if ( (int16_t)dst.val != (uint32_t)dst.val )
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_regs.eflags |= EFLG_OF|EFLG_CF;
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break;
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#ifdef __x86_64__
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case 4:
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dst.val = ((uint64_t)(int32_t)src.val *
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(uint64_t)(int32_t)dst.val);
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if ( (int32_t)dst.val != dst.val )
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_regs.eflags |= EFLG_OF|EFLG_CF;
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break;
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#endif
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default: {
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unsigned long m[2] = { src.val, dst.val };
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if ( imul_dbl(m) )
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_regs.eflags |= EFLG_OF|EFLG_CF;
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dst.val = m[0];
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break;
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}
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}
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emulate_2op_SrcV_srcmem("imul", src, dst, _regs.eflags);
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break;
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case 0xb2: /* lss */
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