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i386: eliminate unsupported CPUs' MCA handling code
Neither Intel P5 nor Winchip are supported by Xen (due to -march=i686 being passed to the compiler), so there is no point in having code for handling their (rudimentary) MCA capabilities. Signed-off-by: Jan Beulich <jbeulich@novell.com>
This commit is contained in:
Keir Fraser committed
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0df83ebb36
5 files changed
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@@ -6,5 +6,3 @@ obj-y += mctelem.o
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obj-y += mce.o
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obj-y += mce_intel.o
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obj-y += non-fatal.o
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obj-$(x86_32) += p5.o
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obj-$(x86_32) += winchip.o
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@@ -616,12 +616,6 @@ void mcheck_init(struct cpuinfo_x86 *c)
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case X86_VENDOR_INTEL:
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switch (c->x86) {
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case 5:
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#ifndef CONFIG_X86_64
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inited = intel_p5_mcheck_init(c);
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#endif
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break;
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case 6:
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case 15:
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inited = intel_mcheck_init(c);
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@@ -629,14 +623,6 @@ void mcheck_init(struct cpuinfo_x86 *c)
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}
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break;
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#ifndef CONFIG_X86_64
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case X86_VENDOR_CENTAUR:
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if (c->x86==5) {
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inited = winchip_mcheck_init(c);
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}
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break;
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#endif
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default:
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break;
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}
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@@ -17,8 +17,6 @@ int amd_k7_mcheck_init(struct cpuinfo_x86 *c);
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int amd_k8_mcheck_init(struct cpuinfo_x86 *c);
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int amd_f10_mcheck_init(struct cpuinfo_x86 *c);
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int intel_p5_mcheck_init(struct cpuinfo_x86 *c);
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int winchip_mcheck_init(struct cpuinfo_x86 *c);
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int intel_mcheck_init(struct cpuinfo_x86 *c);
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void intel_mcheck_timer(struct cpuinfo_x86 *c);
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@@ -1,50 +0,0 @@
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/*
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* P5 specific Machine Check Exception Reporting
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* (C) Copyright 2002 Alan Cox <alan@redhat.com>
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*/
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#include <xen/init.h>
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#include <xen/types.h>
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#include <xen/kernel.h>
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#include <xen/smp.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/msr.h>
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#include "mce.h"
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#include "x86_mca.h"
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/* Machine check handler for Pentium class Intel */
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static void pentium_machine_check(struct cpu_user_regs * regs, long error_code)
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{
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u32 loaddr, hi, lotype;
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rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
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rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
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printk(KERN_EMERG "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n", smp_processor_id(), loaddr, lotype);
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if(lotype&(1<<5))
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printk(KERN_EMERG "CPU#%d: Possible thermal failure (CPU on fire ?).\n", smp_processor_id());
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add_taint(TAINT_MACHINE_CHECK);
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}
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/* Set up machine check reporting for processors with Intel style MCE */
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int intel_p5_mcheck_init(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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/* Default P5 to off as its often misconnected */
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if(mce_disabled != -1)
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return 0;
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x86_mce_vector_register(pentium_machine_check);
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/* Read registers before enabling */
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rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
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rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
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printk(KERN_INFO "Intel old style machine check architecture supported.\n");
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/* Enable MCE */
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set_in_cr4(X86_CR4_MCE);
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printk(KERN_INFO "Intel old style machine check reporting enabled on CPU#%d.\n", smp_processor_id());
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return 1;
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}
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@@ -1,39 +0,0 @@
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/*
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* IDT Winchip specific Machine Check Exception Reporting
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* (C) Copyright 2002 Alan Cox <alan@redhat.com>
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*/
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#include <xen/config.h>
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#include <xen/init.h>
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#include <xen/lib.h>
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#include <xen/types.h>
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#include <xen/kernel.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/msr.h>
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#include "mce.h"
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/* Machine check handler for WinChip C6 */
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static void winchip_machine_check(struct cpu_user_regs * regs, long error_code)
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{
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printk(KERN_EMERG "CPU0: Machine Check Exception.\n");
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add_taint(TAINT_MACHINE_CHECK);
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}
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/* Set up machine check reporting on the Winchip C6 series */
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int winchip_mcheck_init(struct cpuinfo_x86 *c)
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{
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u32 lo, hi;
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wmb();
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x86_mce_vector_register(winchip_machine_check);
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rdmsr(MSR_IDT_FCR1, lo, hi);
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lo|= (1<<2); /* Enable EIERRINT (int 18 MCE) */
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lo&= ~(1<<4); /* Enable MCE */
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wrmsr(MSR_IDT_FCR1, lo, hi);
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set_in_cr4(X86_CR4_MCE);
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printk(KERN_INFO "Winchip machine check reporting enabled on CPU#0.\n");
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return (1);
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}
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