x86/spec-ctrl: Expose BHI_CTRL to guests

The CPUID feature bit signals the presence of the BHI_DIS_S control in
SPEC_CTRL MSR, first available in Intel AlderLake and Sapphire Rapids CPUs

Xen already knows how to context switch MSR_SPEC_CTRL properly between guest
and hypervisor context.

Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
(cherry picked from commit 583f1d0950)
This commit is contained in:
Roger Pau Monné authored and Andrew Cooper committed 2024-04-09 17:16:31 +01:00
1 parent bc7f292b55
commit 0f640366e5
5 files changed
+5 -1

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+1
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@@ -208,6 +208,7 @@ static const char *const str_7d2[32] =
{
[ 0] = "intel-psfd", [ 1] = "ipred-ctrl",
[ 2] = "rrsba-ctrl",
[ 4] = "bhi-ctrl",
};
static const char *const str_m10Al[32] =
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@@ -325,6 +325,7 @@ uint64_t msr_spec_ctrl_valid_bits(const struct cpu_policy *cp)
? (SPEC_CTRL_IPRED_DIS_U | SPEC_CTRL_IPRED_DIS_S) : 0) |
(cp->feat.rrsba_ctrl
? (SPEC_CTRL_RRSBA_DIS_U | SPEC_CTRL_RRSBA_DIS_S) : 0) |
(cp->feat.bhi_ctrl ? SPEC_CTRL_BHI_DIS_S : 0) |
0);
}
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@@ -41,6 +41,7 @@
#define SPEC_CTRL_RRSBA_DIS_U (_AC(1, ULL) << 5)
#define SPEC_CTRL_RRSBA_DIS_S (_AC(1, ULL) << 6)
#define SPEC_CTRL_PSFD (_AC(1, ULL) << 7)
#define SPEC_CTRL_BHI_DIS_S (_AC(1, ULL) << 10)
#define MSR_PRED_CMD 0x00000049
#define PRED_CMD_IBPB (_AC(1, ULL) << 0)
@@ -303,6 +303,7 @@ XEN_CPUFEATURE(SRSO_NO, 11*32+29) /*A Hardware not vulenrable to Spe
XEN_CPUFEATURE(INTEL_PSFD, 13*32+ 0) /*A MSR_SPEC_CTRL.PSFD */
XEN_CPUFEATURE(IPRED_CTRL, 13*32+ 1) /*A MSR_SPEC_CTRL.IPRED_DIS_* */
XEN_CPUFEATURE(RRSBA_CTRL, 13*32+ 2) /*A MSR_SPEC_CTRL.RRSBA_DIS_* */
XEN_CPUFEATURE(BHI_CTRL, 13*32+ 4) /*A MSR_SPEC_CTRL.BHI_DIS_S */
/* Intel-defined CPU features, CPUID level 0x00000007:1.ecx, word 14 */
+1 -1
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@@ -316,7 +316,7 @@ def crunch_numbers(state):
# as dependent features simplifies Xen's logic, and prevents the guest
# from seeing implausible configurations.
IBRSB: [STIBP, SSBD, INTEL_PSFD, EIBRS,
IPRED_CTRL, RRSBA_CTRL],
IPRED_CTRL, RRSBA_CTRL, BHI_CTRL],
IBRS: [AMD_STIBP, AMD_SSBD, PSFD,
IBRS_ALWAYS, IBRS_FAST, IBRS_SAME_MODE],
IBPB: [IBPB_RET, SBPB, IBPB_BRTYPE],
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