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x86/spec-ctrl: Expose BHI_CTRL to guests
The CPUID feature bit signals the presence of the BHI_DIS_S control in
SPEC_CTRL MSR, first available in Intel AlderLake and Sapphire Rapids CPUs
Xen already knows how to context switch MSR_SPEC_CTRL properly between guest
and hypervisor context.
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
(cherry picked from commit 583f1d0950)
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@@ -208,6 +208,7 @@ static const char *const str_7d2[32] =
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{
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[ 0] = "intel-psfd", [ 1] = "ipred-ctrl",
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[ 2] = "rrsba-ctrl",
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[ 4] = "bhi-ctrl",
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};
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static const char *const str_m10Al[32] =
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@@ -325,6 +325,7 @@ uint64_t msr_spec_ctrl_valid_bits(const struct cpu_policy *cp)
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? (SPEC_CTRL_IPRED_DIS_U | SPEC_CTRL_IPRED_DIS_S) : 0) |
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(cp->feat.rrsba_ctrl
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? (SPEC_CTRL_RRSBA_DIS_U | SPEC_CTRL_RRSBA_DIS_S) : 0) |
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(cp->feat.bhi_ctrl ? SPEC_CTRL_BHI_DIS_S : 0) |
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0);
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}
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@@ -41,6 +41,7 @@
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#define SPEC_CTRL_RRSBA_DIS_U (_AC(1, ULL) << 5)
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#define SPEC_CTRL_RRSBA_DIS_S (_AC(1, ULL) << 6)
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#define SPEC_CTRL_PSFD (_AC(1, ULL) << 7)
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#define SPEC_CTRL_BHI_DIS_S (_AC(1, ULL) << 10)
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#define MSR_PRED_CMD 0x00000049
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#define PRED_CMD_IBPB (_AC(1, ULL) << 0)
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@@ -303,6 +303,7 @@ XEN_CPUFEATURE(SRSO_NO, 11*32+29) /*A Hardware not vulenrable to Spe
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XEN_CPUFEATURE(INTEL_PSFD, 13*32+ 0) /*A MSR_SPEC_CTRL.PSFD */
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XEN_CPUFEATURE(IPRED_CTRL, 13*32+ 1) /*A MSR_SPEC_CTRL.IPRED_DIS_* */
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XEN_CPUFEATURE(RRSBA_CTRL, 13*32+ 2) /*A MSR_SPEC_CTRL.RRSBA_DIS_* */
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XEN_CPUFEATURE(BHI_CTRL, 13*32+ 4) /*A MSR_SPEC_CTRL.BHI_DIS_S */
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/* Intel-defined CPU features, CPUID level 0x00000007:1.ecx, word 14 */
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@@ -316,7 +316,7 @@ def crunch_numbers(state):
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# as dependent features simplifies Xen's logic, and prevents the guest
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# from seeing implausible configurations.
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IBRSB: [STIBP, SSBD, INTEL_PSFD, EIBRS,
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IPRED_CTRL, RRSBA_CTRL],
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IPRED_CTRL, RRSBA_CTRL, BHI_CTRL],
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IBRS: [AMD_STIBP, AMD_SSBD, PSFD,
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IBRS_ALWAYS, IBRS_FAST, IBRS_SAME_MODE],
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IBPB: [IBPB_RET, SBPB, IBPB_BRTYPE],
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