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[LINUX] Fix IRQ SMP affinity logic for event channels.
The logic now mimics native x86 behaviour: a request to change
affinity via /proc is held until the next interrupt on that
event channel. So /proc/irq/n/smp_affinity may not change
immediately!
Other notes:
1. CPU-specific interrupts silently ignore requests to change
affinity. For example, resched0, timer0, callfunc0, ...
2. Reading smp_affinity always returns a cpumask containing
a single cpu. An event channel can only be bound to a single
cpu at a time. Neither Xen nor XenLinux implement IRQ
balancing: requires a user-space balancing daemon.
Signed-off-by: Keir Fraser <keir@xensource.com>
This commit is contained in:
kaf24@firebug.cl.cam.ac.uk committed
1 parent
e5617c303f
commit
0f71d8d704
1 file changed
+15
-30
@@ -54,7 +54,8 @@
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static DEFINE_SPINLOCK(irq_mapping_update_lock);
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/* IRQ <-> event-channel mappings. */
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static int evtchn_to_irq[NR_EVENT_CHANNELS] = {[0 ... NR_EVENT_CHANNELS-1] = -1};
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static int evtchn_to_irq[NR_EVENT_CHANNELS] = {
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[0 ... NR_EVENT_CHANNELS-1] = -1 };
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/* Packed IRQ information: binding type, sub-type index, and event channel. */
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static u32 irq_info[NR_IRQS];
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@@ -120,6 +121,11 @@ static inline unsigned long active_evtchns(unsigned int cpu, shared_info_t *sh,
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static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
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{
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int irq = evtchn_to_irq[chn];
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BUG_ON(irq == -1);
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set_native_irq_info(irq, cpumask_of_cpu(cpu));
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clear_bit(chn, (unsigned long *)cpu_evtchn_mask[cpu_evtchn[chn]]);
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set_bit(chn, (unsigned long *)cpu_evtchn_mask[cpu]);
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cpu_evtchn[chn] = cpu;
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@@ -127,7 +133,12 @@ static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
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static void init_evtchn_cpu_bindings(void)
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{
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int i;
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/* By default all event channels notify CPU#0. */
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for (i = 0; i < NR_IRQS; i++)
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set_native_irq_info(i, cpumask_of_cpu(0));
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memset(cpu_evtchn, 0, sizeof(cpu_evtchn));
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memset(cpu_evtchn_mask[0], ~0, sizeof(cpu_evtchn_mask[0]));
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}
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@@ -430,25 +441,14 @@ void unbind_from_irqhandler(unsigned int irq, void *dev_id)
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}
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EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
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#ifdef CONFIG_SMP
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static void do_nothing_function(void *ign)
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{
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}
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#endif
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/* Rebind an evtchn so that it gets delivered to a specific cpu */
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static void rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
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{
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struct evtchn_bind_vcpu bind_vcpu;
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int evtchn;
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int evtchn = evtchn_from_irq(irq);
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spin_lock(&irq_mapping_update_lock);
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evtchn = evtchn_from_irq(irq);
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if (!VALID_EVTCHN(evtchn)) {
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spin_unlock(&irq_mapping_update_lock);
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if (!VALID_EVTCHN(evtchn))
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return;
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}
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/* Send future instances of this interrupt to other vcpu. */
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bind_vcpu.port = evtchn;
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@@ -461,21 +461,6 @@ static void rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
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*/
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if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
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bind_evtchn_to_cpu(evtchn, tcpu);
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spin_unlock(&irq_mapping_update_lock);
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/*
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* Now send the new target processor a NOP IPI. When this returns, it
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* will check for any pending interrupts, and so service any that got
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* delivered to the wrong processor by mistake.
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*
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* XXX: The only time this is called with interrupts disabled is from
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* the hotplug/hotunplug path. In that case, all cpus are stopped with
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* interrupts disabled, and the missed interrupts will be picked up
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* when they start again. This is kind of a hack.
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*/
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if (!irqs_disabled())
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smp_call_function(do_nothing_function, NULL, 0, 0);
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}
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@@ -597,8 +582,8 @@ static unsigned int startup_pirq(unsigned int irq)
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pirq_query_unmask(irq_to_pirq(irq));
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bind_evtchn_to_cpu(evtchn, 0);
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evtchn_to_irq[evtchn] = irq;
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bind_evtchn_to_cpu(evtchn, 0);
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irq_info[irq] = mk_irq_info(IRQT_PIRQ, irq, evtchn);
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out:
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