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i386: fix full-value calculation of wrmsr handling for pv guests
The MSR value must be held in a 64-bit variable, not an unsigned long. Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
This commit is contained in:
Keir Fraser committed
1 parent
41859f6925
commit
109cae48ec
1 file changed
+15
-12
+15
-12
@@ -1677,7 +1677,7 @@ static int is_cpufreq_controller(struct domain *d)
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static int emulate_privileged_op(struct cpu_user_regs *regs)
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{
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struct vcpu *v = current;
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unsigned long *reg, eip = regs->eip, res;
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unsigned long *reg, eip = regs->eip;
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u8 opcode, modrm_reg = 0, modrm_rm = 0, rep_prefix = 0, lock = 0, rex = 0;
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enum { lm_seg_none, lm_seg_fs, lm_seg_gs } lm_ovr = lm_seg_none;
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int rc;
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@@ -1696,7 +1696,7 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
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unsigned long code_base, code_limit;
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char io_emul_stub[32];
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void (*io_emul)(struct cpu_user_regs *) __attribute__((__regparm__(1)));
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u32 l, h, eax, edx;
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u32 l, h;
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if ( !read_descriptor(regs->cs, v, regs,
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&code_base, &code_limit, &ar,
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@@ -2075,7 +2075,8 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
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}
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break;
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case 0x21: /* MOV DR?,<reg> */
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case 0x21: /* MOV DR?,<reg> */ {
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unsigned long res;
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opcode = insn_fetch(u8, code_base, eip, code_limit);
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if ( opcode < 0xc0 )
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goto fail;
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@@ -2086,6 +2087,7 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
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goto fail;
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*reg = res;
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break;
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}
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case 0x22: /* MOV <reg>,CR? */
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opcode = insn_fetch(u8, code_base, eip, code_limit);
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@@ -2146,10 +2148,10 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
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goto fail;
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break;
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case 0x30: /* WRMSR */
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eax = regs->eax;
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edx = regs->edx;
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res = ((u64)edx << 32) | eax;
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case 0x30: /* WRMSR */ {
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u32 eax = regs->eax;
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u32 edx = regs->edx;
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u64 val = ((u64)edx << 32) | eax;
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switch ( (u32)regs->ecx )
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{
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#ifdef CONFIG_X86_64
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@@ -2158,21 +2160,21 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
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goto fail;
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if ( wrmsr_safe(MSR_FS_BASE, eax, edx) )
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goto fail;
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v->arch.guest_context.fs_base = res;
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v->arch.guest_context.fs_base = val;
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break;
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case MSR_GS_BASE:
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if ( is_pv_32on64_vcpu(v) )
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goto fail;
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if ( wrmsr_safe(MSR_GS_BASE, eax, edx) )
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goto fail;
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v->arch.guest_context.gs_base_kernel = res;
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v->arch.guest_context.gs_base_kernel = val;
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break;
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case MSR_SHADOW_GS_BASE:
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if ( is_pv_32on64_vcpu(v) )
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goto fail;
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if ( wrmsr_safe(MSR_SHADOW_GS_BASE, eax, edx) )
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goto fail;
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v->arch.guest_context.gs_base_user = res;
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v->arch.guest_context.gs_base_user = val;
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break;
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#endif
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case MSR_K7_FID_VID_STATUS:
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@@ -2215,7 +2217,7 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
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if ( !IS_PRIV(v->domain) )
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break;
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if ( (rdmsr_safe(MSR_FAM10H_MMIO_CONF_BASE, l, h) != 0) ||
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(((((u64)h << 32) | l) ^ res) &
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(((((u64)h << 32) | l) ^ val) &
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~( FAM10H_MMIO_CONF_ENABLE |
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(FAM10H_MMIO_CONF_BUSRANGE_MASK <<
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FAM10H_MMIO_CONF_BUSRANGE_SHIFT) |
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@@ -2247,7 +2249,7 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
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if ( wrmsr_hypervisor_regs(regs->ecx, eax, edx) )
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break;
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rc = mce_wrmsr(regs->ecx, res);
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rc = mce_wrmsr(regs->ecx, val);
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if ( rc < 0 )
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goto fail;
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if ( rc )
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@@ -2262,6 +2264,7 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
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break;
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}
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break;
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}
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case 0x31: /* RDTSC */
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rdtsc(regs->eax, regs->edx);
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