xen/arm64: head: Introduce a helper to flush local TLBs

Instead of repeating the same sequence of instructions to flush the TLBs
in various places, introduce a macro flush_xen_tlb_local and make use of
it. This is similar to what was done for arm32 by the commit:
dea9dddece

This is also making the flush sequence in enable_mmu more clear and
consistent.

Signed-off-by: Michal Orzel <michal.orzel@amd.com>
Reviewed-by: Luca Fancellu <luca.fancellu@arm.com>
Acked-by: Stefano Stabellini <sstabellini@kernel.org>
Reviewed-by: Julien Grall <jgrall@amazon.com>
This commit is contained in:
Michal Orzel authored and Julien Grall committed 2023-08-09 12:00:12 +01:00
1 parent a8a7c33e7d
commit 15601eed05
1 file changed
+16 -15
+16 -15
View File
@@ -136,6 +136,18 @@
add \xb, \xb, x20
.endm
/*
* Flush local TLBs
*
* See asm/arm64/flushtlb.h for the explanation of the sequence.
*/
.macro flush_xen_tlb_local
dsb nshst
tlbi alle2
dsb nsh
isb
.endm
.section .text.header, "ax", %progbits
/*.aarch64*/
@@ -721,8 +733,7 @@ enable_mmu:
* The state of the TLBs is unknown before turning on the MMU.
* Flush them to avoid stale one.
*/
tlbi alle2 /* Flush hypervisor TLBs */
dsb nsh
flush_xen_tlb_local
/* Write Xen's PT's paddr into TTBR0_EL2 */
msr TTBR0_EL2, x4
@@ -786,11 +797,7 @@ remove_identity_mapping:
str xzr, [x0, x1, lsl #3]
identity_mapping_removed:
/* See asm/arm64/flushtlb.h for the explanation of the sequence. */
dsb nshst
tlbi alle2
dsb nsh
isb
flush_xen_tlb_local
ret
ENDPROC(remove_identity_mapping)
@@ -872,14 +879,8 @@ ENTRY(switch_ttbr_id)
msr SCTLR_EL2, x1
isb
/*
* 3) Flush the TLBs.
* See asm/arm64/flushtlb.h for the explanation of the sequence.
*/
dsb nshst
tlbi alle2
dsb nsh
isb
/* 3) Flush the TLBs */
flush_xen_tlb_local
/* 4) Update the TTBR */
msr TTBR0_EL2, x0
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