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x86: blacklist new AMD CPUID bits for PV domains
there are some new CPUID bits (and leaves) which Dom0 and PV domains should not see to avoid trouble, since we don't emulate the features. The most prominent one is a topology leaf, which contains information specific to the physical CPU, not the virtual one. To avoid confusion (and possibly crashes) due to a confused Dom0 scheduler simply disable these bits. Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Keir Fraser <keir@xen.org>
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@@ -427,12 +427,17 @@ static void xc_cpuid_pv_policy(
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clear_bit(X86_FEATURE_IBS, regs[2]);
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clear_bit(X86_FEATURE_SKINIT, regs[2]);
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clear_bit(X86_FEATURE_WDT, regs[2]);
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clear_bit(X86_FEATURE_LWP, regs[2]);
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clear_bit(X86_FEATURE_NODEID_MSR, regs[2]);
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clear_bit(X86_FEATURE_TOPOEXT, regs[2]);
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break;
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case 5: /* MONITOR/MWAIT */
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case 0xa: /* Architectural Performance Monitor Features */
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case 0xd: /* XSAVE */
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case 0x8000000a: /* SVM revision and features */
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case 0x8000001b: /* Instruction Based Sampling */
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case 0x8000001c: /* Light Weight Profiling */
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case 0x8000001e: /* Extended topology reporting */
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regs[0] = regs[1] = regs[2] = regs[3] = 0;
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break;
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}
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@@ -802,11 +802,16 @@ static void pv_cpuid(struct cpu_user_regs *regs)
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__clear_bit(X86_FEATURE_IBS % 32, &c);
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__clear_bit(X86_FEATURE_SKINIT % 32, &c);
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__clear_bit(X86_FEATURE_WDT % 32, &c);
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__clear_bit(X86_FEATURE_LWP % 32, &c);
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__clear_bit(X86_FEATURE_NODEID_MSR % 32, &c);
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__clear_bit(X86_FEATURE_TOPOEXT % 32, &c);
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break;
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case 5: /* MONITOR/MWAIT */
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case 0xa: /* Architectural Performance Monitor Features */
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case 0x8000000a: /* SVM revision and features */
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case 0x8000001b: /* Instruction Based Sampling */
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case 0x8000001c: /* Light Weight Profiling */
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case 0x8000001e: /* Extended topology reporting */
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a = b = c = d = 0;
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break;
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default:
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