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x86/vvmx: Use hvm_cr4_guest_valid_bits() to calculate MSR_IA32_VMX_CR4_FIXED1
Reuse the logic in hvm_cr4_guest_valid_bits() instead of duplicating it. This fixes a bug to do with the handling of X86_CR4_PCE. The RDPMC instruction predate the architectural performance feature, and has been around since the P6. X86_CR4_PCE is like X86_CR4_TSD and only controls whether RDPMC is available at cpl!=0, not whether RDPMC is generally unavailable. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Kevin Tian <kevin.tian@intel.com> Reviewed-by: Jan Beulich <jbeulich@suse.com>
This commit is contained in:
Andrew Cooper committed
1 parent
f0b043042e
commit
1b6e063f5e
1 file changed
+3
-55
@@ -1840,16 +1840,12 @@ int nvmx_handle_invvpid(struct cpu_user_regs *regs)
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int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
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{
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struct vcpu *v = current;
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unsigned int eax, ebx, ecx, edx;
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struct domain *d = v->domain;
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u64 data = 0, host_data = 0;
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int r = 1;
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if ( !nestedhvm_enabled(v->domain) )
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return 0;
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/* VMX capablity MSRs are available only when guest supports VMX. */
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hvm_cpuid(0x1, NULL, NULL, &ecx, &edx);
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if ( !(ecx & cpufeat_mask(X86_FEATURE_VMX)) )
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if ( !nestedhvm_enabled(d) || !d->arch.cpuid->basic.vmx )
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return 0;
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/*
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@@ -1995,55 +1991,7 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
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data = X86_CR4_VMXE;
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break;
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case MSR_IA32_VMX_CR4_FIXED1:
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if ( edx & cpufeat_mask(X86_FEATURE_VME) )
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data |= X86_CR4_VME | X86_CR4_PVI;
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if ( edx & cpufeat_mask(X86_FEATURE_TSC) )
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data |= X86_CR4_TSD;
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if ( edx & cpufeat_mask(X86_FEATURE_DE) )
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data |= X86_CR4_DE;
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if ( edx & cpufeat_mask(X86_FEATURE_PSE) )
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data |= X86_CR4_PSE;
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if ( edx & cpufeat_mask(X86_FEATURE_PAE) )
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data |= X86_CR4_PAE;
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if ( edx & cpufeat_mask(X86_FEATURE_MCE) )
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data |= X86_CR4_MCE;
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if ( edx & cpufeat_mask(X86_FEATURE_PGE) )
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data |= X86_CR4_PGE;
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if ( edx & cpufeat_mask(X86_FEATURE_FXSR) )
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data |= X86_CR4_OSFXSR;
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if ( edx & cpufeat_mask(X86_FEATURE_SSE) )
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data |= X86_CR4_OSXMMEXCPT;
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if ( ecx & cpufeat_mask(X86_FEATURE_VMX) )
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data |= X86_CR4_VMXE;
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if ( ecx & cpufeat_mask(X86_FEATURE_SMX) )
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data |= X86_CR4_SMXE;
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if ( ecx & cpufeat_mask(X86_FEATURE_PCID) )
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data |= X86_CR4_PCIDE;
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if ( ecx & cpufeat_mask(X86_FEATURE_XSAVE) )
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data |= X86_CR4_OSXSAVE;
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hvm_cpuid(0x0, &eax, NULL, NULL, NULL);
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switch ( eax )
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{
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default:
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hvm_cpuid(0xa, &eax, NULL, NULL, NULL);
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/* Check whether guest has the perf monitor feature. */
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if ( (eax & 0xff) && (eax & 0xff00) )
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data |= X86_CR4_PCE;
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/* fall through */
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case 0x7 ... 0x9:
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ecx = 0;
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hvm_cpuid(0x7, NULL, &ebx, &ecx, NULL);
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if ( ebx & cpufeat_mask(X86_FEATURE_FSGSBASE) )
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data |= X86_CR4_FSGSBASE;
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if ( ebx & cpufeat_mask(X86_FEATURE_SMEP) )
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data |= X86_CR4_SMEP;
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if ( ebx & cpufeat_mask(X86_FEATURE_SMAP) )
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data |= X86_CR4_SMAP;
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/* fall through */
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case 0x0 ... 0x6:
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break;
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}
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data = hvm_cr4_guest_valid_bits(v, 0);
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break;
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case MSR_IA32_VMX_MISC:
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/* Do not support CR3-target feature now */
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