vtd: improve IOMMU TLB flush

Do not limit PSI flushes to order 0 pages, in order to avoid doing a
full TLB flush if the passed in page has an order greater than 0 and
is aligned. Should increase the performance of IOMMU TLB flushes when
dealing with page orders greater than 0.

This is part of XSA-321.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
master commit: 5fe515a0fe
master date: 2020-07-07 14:37:46 +0200
This commit is contained in:
Jan Beulich committed 2020-07-07 15:01:57 +02:00
1 parent 2b34d8cd73
commit 1c7a98cab9
1 file changed
+3 -2
+3 -2
View File
@@ -570,13 +570,14 @@ static int __must_check iommu_flush_iotlb(struct domain *d, dfn_t dfn,
if ( iommu_domid == -1 )
continue;
if ( page_count != 1 || dfn_eq(dfn, INVALID_DFN) )
if ( !page_count || (page_count & (page_count - 1)) ||
dfn_eq(dfn, INVALID_DFN) || !IS_ALIGNED(dfn_x(dfn), page_count) )
rc = iommu_flush_iotlb_dsi(iommu, iommu_domid,
0, flush_dev_iotlb);
else
rc = iommu_flush_iotlb_psi(iommu, iommu_domid,
dfn_to_daddr(dfn),
PAGE_ORDER_4K,
get_order_from_pages(page_count),
!dma_old_pte_present,
flush_dev_iotlb);
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